Electronically programmable and erasable memory device having floating gate electrode with a unique distribution of impurity concentration

Claim 1

An electrically programmable and erasable memory device comprising a semiconductor substrate of one conductivity type, source and drain regions of the opposite conductivity type formed in a major surface of said substrate, a channel region positioned in said major surface of said substrate between said source and drain regions, a floating gate electrode made of polycrystalline silicon, a first gate insulating film positioned between said floating gate electrode and said major surface of said substrate, a second gate insulating film formed on said floating gate electrode, and a control gate electrode formed on said second gate insulating film, said first gate insulating film including a partially thin portion above a part of said drain region, and said floating gate being a double film structure including a first polycrystalline silicon film having a low impurity concentration and being attached at its bottom surface to said first gate insulating film including said thin portion, and a second polycrystalline silicon film having a higher impurity concentration than said first polycrystalline silicon film, said second polycrystalline silicon film being formed on said first polycrystalline silicon film and being attached at its upper surface to said second gate insulating film, said first and second polycrystalline silicon films having the same plan shape and overlying parts of said source and drain regions and entire parts of said channel region, whereby a sufficient amount of carriers can be stored in said floating gate electrode even after writing and erasing operations have been repeated more than 10 5 times.