US5794026A
Expired / Lapsed
US
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Microprocessor having expedited execution of condition dependent instructions
Assignee: VIA Cyrix Inc
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Filing: 1993-10-18
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Granted: 1998-08-11
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Expires: 2013-10-18
Abstract
Abstract A processor architecture and methodology for executing a condition dependent instruction over a plurality of execution stages in a microprocessor. The microprocessor includes a memory for storing microinstructions. The method involves various steps. In one step, an instruction is received. In another step, a first microinstruction is issued from the memory. This first microinstruction comprises a control and a base address. In yet another step, a secondary address is determined, external from the memory, by evaluating a plurality of predetermined data. In a still another step, the base address and the secondary address are combined to form a destination address in response to the control signal, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.
Inventors
- 👤 Mark W. Hervin
- 👤 Ronald S. McMahon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:22
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/265; G06F9/28
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
121 words
A method of executing an instruction over a plurality of execution stages in a microprocessor having a memory storing microinstructions, comprising the steps of: receiving an instruction; issuing a first microinstruction from the memory in response to receiving the instruction, the first microinstruction comprising: a control signal; and a base address; determining a secondary address by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory; and combining the base address and the already-determined secondary address to form a destination address only in response to the control signal, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.
Claim 2
Independent Claim
121 words
A method of executing an instruction over a plurality of execution stages in a microprocessor having a memory storing microinstructions, comprising the steps of: receiving an instruction; issuing a first microinstruction from the memory in response to receiving the instruction, the first microinstruction comprising: a control signal; and a base address; determining a secondary address by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory; and combining the base address and the already-determined secondary address to form a destination address only in response to the control signal, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.
Claim 3
Dependent Claim
31 words
The method of claim 1 wherein the microprocessor operates during clock cycles, and wherein said step of determining a secondary address comprises determining a secondary address in a single clock cycle.
Claim 4
Dependent Claim
14 words
The method of claim 1 wherein said determining step occurs before said issuing step.
Claim 5
Dependent Claim
53 words
The method of claim 1 wherein the destination address comprises an upper and lower portion, and wherein said combining step comprises concatenating the base address and the secondary address, wherein the base address comprises the upper portion of the destination address and the secondary address comprises the lower portion of the destination address.
Claim 6
Dependent Claim
32 words
The method of claim 1 wherein the microprocessor includes mode bits and history bits, and wherein said step of determining a secondary address comprises evaluating the mode bits and the history bits.
Claim 7
Dependent Claim
32 words
The method of claim 1 wherein said step of receiving an instruction comprising receiving an X86 instruction set instruction, and wherein said step of determining a secondary address comprises evaluating descriptor bits.
Claim 8
Dependent Claim
30 words
The method of claim 1 wherein said step of determining a secondary address comprises determining a completion signal, the completion signal indicating completion of the execution stages of the instruction.
Claim 9
Dependent Claim
18 words
The method of claim 1 wherein said step of receiving an instruction comprises receiving a condition dependent instruction.
Claim 10
Dependent Claim
19 words
The method of claim 1 wherein said step of receiving an instruction comprises receiving a change of flow instruction.
Claim 11
Independent Claim
109 words
A method of executing an instruction over a plurality of execution stages in a microprocessor having a memory storing microinstructions, comprising the steps of: receiving an instruction; issuing a first microinstruction from the memory corresponding to the instruction, the first microinstruction comprising a control signal; and forming a destination address only in response to the control signal, the destination address comprising an address component formed by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.
Claim 12
Independent Claim
109 words
A method of executing an instruction over a plurality of execution stages in a microprocessor having a memory storing microinstructions, comprising the steps of: receiving an instruction; issuing a first microinstruction from the memory corresponding to the instruction, the first microinstruction comprising a control signal; and forming a destination address only in response to the control signal, the destination address comprising an address component formed by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory, wherein the destination address identifies a second microinstruction in the memory to execute a successive stage for the received instruction.
Claim 13
Dependent Claim
52 words
The method of claim 10 wherein said address component comprises a first address component, and said forming step further comprises: forming a second address portion of the destination address from a portion of the first microinstruction; and combining the first address portion and the second address portion to form the destination address.
Claim 14
Dependent Claim
25 words
The method of claim 11 wherein said combining step comprises concatenating the first address portion and the second address portion to form the destination address.
Claim 15
Dependent Claim
39 words
The method of claim 12 wherein the destination address comprises an upper and lower portion, and wherein said concatenating step comprises concatenating the first address portion as the lower portion and the second address portion as the upper portion.
Claim 16
Independent Claim
88 words
A method of executing an instruction over a plurality of execution stages in a microprocessor having a memory storing microinstructions, comprising the steps of: receiving an instruction; issuing a microinstruction from the memory, the microinstruction comprising a control signal; forming a completion signal by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory; and responsive to the control signal, issuing the already-determined completion signal indicating completion of the execution stages of the received instruction.
Claim 17
Independent Claim
88 words
A method of executing an instruction over a plurality of execution stages in a microprocessor having a memory storing microinstructions, comprising the steps of: receiving an instruction; issuing a microinstruction from the memory, the microinstruction comprising a control signal; forming a completion signal by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory; and responsive to the control signal, issuing the already-determined completion signal indicating completion of the execution stages of the received instruction.
Claim 18
Dependent Claim
37 words
The method of claim 14 wherein a successive instruction follows the received instruction, and further comprising the step of commencing a first execution stage of the successive instruction in response said step of issuing a completion signal.
Claim 19
Dependent Claim
117 words
A processor operable to execute instructions over a plurality of execution stages, comprising: a memory for storing microinstructions; circuitry for receiving an instruction; circuitry for issuing a first microinstruction from said memory, the first microinstruction comprising: a control signal; and a base address; circuitry for determining a secondary address, by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory; and circuitry for combining the base address and the already-determined secondary address to form a destination address only in response to the control signal, wherein the destination address identifies a second microinstruction in the memory for executing a successive stage for the received instruction.
Claim 20
Dependent Claim
117 words
A processor operable to execute instructions over a plurality of execution stages, comprising: a memory for storing microinstructions; circuitry for receiving an instruction; circuitry for issuing a first microinstruction from said memory, the first microinstruction comprising: a control signal; and a base address; circuitry for determining a secondary address, by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory; and circuitry for combining the base address and the already-determined secondary address to form a destination address only in response to the control signal, wherein the destination address identifies a second microinstruction in the memory for executing a successive stage for the received instruction.
Claim 21
Dependent Claim
56 words
The processor of claim 16 wherein the destination address comprises an upper and lower portion, and wherein said circuitry for combining comprises circuitry for concatenating the base address and the secondary address, wherein the base address comprises the upper portion of the destination address and the secondary address comprises the lower portion of the destination address.
Claim 22
Dependent Claim
34 words
The processor of claim 16 wherein the microprocessor includes mode bits and history bits, and wherein said circuitry for determining a secondary address comprises circuitry for receiving said mode bits and said history bits.
Claim 23
Dependent Claim
37 words
The processor of claim 16 wherein said circuitry for receiving an instruction comprises circuitry for receiving an X86 instruction set instruction, and wherein said circuitry for determining a secondary address comprises circuitry for receiving said history bits.
Claim 24
Dependent Claim
108 words
A processor for executing instructions over a plurality of execution stages, comprising: a memory for storing microinstructions; circuitry for receiving an instruction; circuitry for issuing a first microinstruction from the memory, the first microinstruction comprising a control signal; and circuitry for forming a destination address, the destination address comprising an address component that is only issued in response to the control signal, and formed by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory, wherein the destination address identifies a second microinstruction in said memory to execute a successive stage for the received instruction.
Claim 25
Dependent Claim
108 words
A processor for executing instructions over a plurality of execution stages, comprising: a memory for storing microinstructions; circuitry for receiving an instruction; circuitry for issuing a first microinstruction from the memory, the first microinstruction comprising a control signal; and circuitry for forming a destination address, the destination address comprising an address component that is only issued in response to the control signal, and formed by evaluating, prior to issuing said first microinstruction's control signal, a plurality of predetermined data that is external to and independent of the memory, wherein the destination address identifies a second microinstruction in said memory to execute a successive stage for the received instruction.
Claim 26
Dependent Claim
57 words
The processor of claim 20 wherein said address component comprises a first address component, and said circuitry for forming further comprises: circuitry for forming a second address portion of the destination address from a portion of the first microinstruction; and circuitry for combining the first address portion and the second address portion to form the destination address.
Claim 27
Dependent Claim
28 words
The processor of claim 21 wherein said circuitry for combining comprises circuitry for concatenating the first address portion and the second address portion to form the destination address.
Claim 28
Dependent Claim
42 words
The processor of claim 22 wherein the destination address comprises an upper and lower portion, and wherein said circuitry for concatenating comprises circuitry for concatenating the first address portion as the lower portion and the second address portion as the upper portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-10 | 2002-02-09 | 2002-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-10 | 2006-02-09 | 2006-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-10 | 2010-02-09 | 2010-08-11 | $7700.00 | Window Closed / Lapsed |