Computer system having mixed macrocode and microcode instruction execution

Claim 2

A digital computer system, comprising: a central processor for executing machine instructions; a microcode memory for storing machine instructions; a macro-instruction decode table located in said microcode memory for decoding macro instructions presented to the central processor, wherein said decode table con­tains machine instructions of two classes, wherein instructions of the first class are directly decodable and executable by the central processor, and wherein instructions of the second class point to microcode routines in said microcode memory; and a decoder coupled to said central processor and to said microcode memory for decoding instructions of the first class and causing their direct execution by the cen­tral processor, and for initiating execution of microcode routines corresponding to instructions of the second class.

Claim 3

A digital computer system, comprising: a central processor for executing machine instructions; a main memory coupled to said central processor and containing machine instruc­tions to be executed by said central processor; a microcode memory coupled to said central processor and containing microcode routines corresponding to machine instructions; a macro-decode table coupled to said central processor and having a plurality of entries, wherein each entry corresponds to a machine instruction, wherein each entry is classified as belonging to one of a first or second set, and wherein machine instructions to be executed by said central processor index an entry in said macro-decode table; and a decoder coupled to said central processor, said microcode memory, and said macro-decode table, wherein entries in said macro-decode table which are contained in the first set define directly executable machine instructions which are decoded by said decoder when such entries are indexed by a current machine instruction, and wherein entries in said macro-decode table which are contained in the second set identify microcode routines corresponding to machine instructions, and said decoder causes the corresponding microcode routine to be executed when such entries are indexed by a current machine instruction; wherein machine instructions from said main memory are accessed by said central processor and used to index entries in said macro-decode table, whereby machine instructions corresponding to first set table entries are executed directly and machine instructions corresponding to second set table entries cause execution of a microcode routine.

Claim 4

A digital computer system, comprising: a central processor for executing machine instructions; a main memory coupled to said central processor and containing machine instruc­tions to be executed by said central processor; a microcode memory coupled to said central processor and containing microcode routines corresponding to machine instructions; a macro-decode table coupled to said central processor and having a plurality of entries, wherein each entry corresponds to a machine instruction, wherein each entry is classified as belonging to one of a first or second set, and wherein machine instructions to be executed by said central processor index an entry in said macro-decode table; and a decoder coupled to said central processor, said microcode memory, and said macro-decode table, wherein entries in said macro-decode table which are contained in the first set define directly executable machine instructions which are decoded by said decoder when such entries are indexed by a current machine instruction, and wherein entries in said macro-decode table which are contained in the second set identify microcode routines corresponding to machine instructions, and said decoder causes the corresponding microcode routine to be executed when such entries are indexed by a current machine instruction; wherein machine instructions from said main memory are accessed by said central processor and used to index entries in said macro-decode table, whereby machine instructions corresponding to first set table entries are executed directly and machine instructions corresponding to second set table entries cause execution of a microcode routine.

Claim 9

The method of Claim 4, wherein step (b) comprises the steps of: (b.1) using the machine instruction to index a decode table having class bits which indicate whether the machine instruction is directly executable; and (b.2) reading the class bits for the machine instruction.

Claim 10

In a computer system having pipelined execution of instructions, the method for executing instructions comprising the steps of: (a) fetching a next machine instruction; (b) if the next machine instruction is directly executable, executing such instruc­tion and returning to step (a); (c) if the next machine instruction is not directly executable, (c.1) saving the current state of the instruction pipeline, (c.2) jumping to a microcode routine corresonding to the next machine instruc­tion, and executing such microcode routine, (c.3) restoring the state of the instruction pipeline which was saved in step (c.1), and (c.4) returning to step (a).

Claim 11

In a computer system having pipelined execution of instructions, the method for executing instructions comprising the steps of: (a) fetching a next machine instruction; (b) if the next machine instruction is directly executable, executing such instruc­tion and returning to step (a); (c) if the next machine instruction is not directly executable, (c.1) saving the current state of the instruction pipeline, (c.2) jumping to a microcode routine corresonding to the next machine instruc­tion, and executing such microcode routine, (c.3) restoring the state of the instruction pipeline which was saved in step (c.1), and (c.4) returning to step (a).

Claim 12

An instruction prefetch queue for a computer system, comprising: an instruction queue of length n for holding macroinstructions to be performed; a program counter queue of length n for holding program counters corresonding to the macroinstructions in said instruction queue; a pipeline controller coupled to said instruction queue for selecting an instruction from the queue and using it to generate a microistruction address, wherein instruc­tions are removed from the queue only when a microcode instruction corresponding to that instruction is returned to a processor for execution, whereby the instruction selected for generating a microinstruction address may not be at the head of said instruction queue.

Claim 13

An instruction prefetch queue for a computer system, comprising: an instruction queue of length n for holding macroinstructions to be performed; a program counter queue of length n for holding program counters corresonding to the macroinstructions in said instruction queue; a pipeline controller coupled to said instruction queue for selecting an instruction from the queue and using it to generate a microistruction address, wherein instruc­tions are removed from the queue only when a microcode instruction corresponding to that instruction is returned to a processor for execution, whereby the instruction selected for generating a microinstruction address may not be at the head of said instruction queue.

Claim 14

The queue of Claim 7, wherein said pipieline controller can access any of the first 3 instructions in the queue.

Claim 15

The queue of Claim 7, further comprising: a multiplexer coupled to said instruction queue and to said pipeline controller, wherein instructions in said queue are connected to the data inputs of said multiplexer, and wherein said pipeline controller accesses the instructions by controlling the control inputs to said multiplexer.