EP0223150A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Information processing apparatus
Assignee: Hitachi Ltd
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Filing: 1986-11-04
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Granted: —
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Expires: 2006-11-04
Abstract
Abstract An information processing apparatus having a buffer register (l) for pre-fetching a plurality of instructions and executing one instruction after another by reading them from the buffer registers, is provided with a first instruction decode start determination unit (50, 52, 55, 57) for register type instructions and a second instruction decode start determination unit (50-52, 56, 58) for non-register type instructions, provided separately from the first unit, whereby 0.5 cycle after a register type instruction starts being decoded, or l cycle after a non-register type instruction starts being decoded, the next instruction starts to be decoded. By decoding a register type instruction at high speed, it becomes possible to execute a branch instruction at high speed.
Inventors
- 👤 Kenichi Wada
- 👤 Kazunori Kuriyama
- 👤 Akira Yamaoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 11:28
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/3873; G06F9/3802; G06F9/3836
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
431 words
An information processing apparatus comprising: storage means (402, 405) for storing at least instructions and data; instruction control means (40l) coupled to said storage means, for controlling the execution of instructions read out of said storage means, said instruction control means including a general purpose register (3), instruction read means (l, 2, 6, l0-l2) for reading said instructions out of said storage means, decoding means (l3) for decoding said instructions read out of said storage means, data read means (306, 5) for reading out of said storage means and said general purpose register data necessary for executing said decoded instructions and an instruction queue (4) for storing said decoded instructions; and execution control means (403) coupled to said storage means and said instruction control means, for arithemetically processing said data read out by said data read means on the basis of said decoded instructions sent from said instruction queue, said instruction read means further including: a buffer register (l) coupled to said storage means, for pre-fetching a plurality of instructions out of said storage means; instruction selection and hold means (2, 6, l0, ll) for selecting instructions one by one from said plurality of instructions so as to send each selected instruction to said decoding means; and decode start control means (l2) including instruction type determination means (50) for determining whether an instruction put under decoding is a first type instruction or a second type instruction, said first type instruction being of the type wherein all the data necessary for executing said first type instruction are stored in said general purpose register and said second type instruction being of the type wherein at least one of data necessary for executing said second type instruction is stored in said storage means, a first determination means (55, 57, 59) for determining, when an instruction selected by said instruction selection and hold means is said first type instruction, whether decoding of an instruction to be decoded following said first type instruction is ready to start and a second determination means (5l, 56, 58) for determining, when an instruction selected by said instruction selection and hold means is said second type instruction, whether decoding of an instruction to be decoded following said second type instruction is ready to start, said first determination means being quicker than said second determination means in completing said determination, said decode start control means controlling said instruction selection and hold means so that an instruction to be decoded following an instruction which is under decoding is sent to said decoding means in response to said first and second determination means.
Claim 2
Dependent Claim
431 words
An information processing apparatus comprising: storage means (402, 405) for storing at least instructions and data; instruction control means (40l) coupled to said storage means, for controlling the execution of instructions read out of said storage means, said instruction control means including a general purpose register (3), instruction read means (l, 2, 6, l0-l2) for reading said instructions out of said storage means, decoding means (l3) for decoding said instructions read out of said storage means, data read means (306, 5) for reading out of said storage means and said general purpose register data necessary for executing said decoded instructions and an instruction queue (4) for storing said decoded instructions; and execution control means (403) coupled to said storage means and said instruction control means, for arithemetically processing said data read out by said data read means on the basis of said decoded instructions sent from said instruction queue, said instruction read means further including: a buffer register (l) coupled to said storage means, for pre-fetching a plurality of instructions out of said storage means; instruction selection and hold means (2, 6, l0, ll) for selecting instructions one by one from said plurality of instructions so as to send each selected instruction to said decoding means; and decode start control means (l2) including instruction type determination means (50) for determining whether an instruction put under decoding is a first type instruction or a second type instruction, said first type instruction being of the type wherein all the data necessary for executing said first type instruction are stored in said general purpose register and said second type instruction being of the type wherein at least one of data necessary for executing said second type instruction is stored in said storage means, a first determination means (55, 57, 59) for determining, when an instruction selected by said instruction selection and hold means is said first type instruction, whether decoding of an instruction to be decoded following said first type instruction is ready to start and a second determination means (5l, 56, 58) for determining, when an instruction selected by said instruction selection and hold means is said second type instruction, whether decoding of an instruction to be decoded following said second type instruction is ready to start, said first determination means being quicker than said second determination means in completing said determination, said decode start control means controlling said instruction selection and hold means so that an instruction to be decoded following an instruction which is under decoding is sent to said decoding means in response to said first and second determination means.
Claim 3
Dependent Claim
326 words
An information processing apparatus according to claim l, wherein said instruction selection and hold means includes instruction selection means (l0) for selecting one instruction at a time from said buffer register and instruction register (2) for storing said one instruction, wherein said instruction control means further includes first means (20) for monitoring the validity of said instruction register and generating a first signal (30l) when valid, second means (40) for monitoring said instruction queue for vacancy thereof and generating a second signal (303) when vacant, third means (4l) for monitoring the validity of a register included in said general purpose register and designated by said first type register and generating a third signal when valid and fourth means (2l) for monitoring whether data read request to said storage means is not inhibited and generating a fourth signal (305) when not inhibited, wherein said first determination means includes first AND gate means (57) for logically ANDing an output signal of said instruction type determination means, representing said instruction put under decoding being said first type instruction, said first signal and said second signal and a first flip-flop (55) connected to the output of said AND gate means for generating a first decode start signal in response to a first clock signal (T₁, T₃), and wherein said second determination means includes second AND gate means (58) for logically ANDing an output signal of said instruction type determination means (58), representing said instruction put under decoding being said second type instruction and said first to fourth signals, a second flip-flop (56), connected to the output of said second flip-flop, for generating a second decode start signal in response to second clock signal, said instruction selection means selecting an instruction to be decoded in response to said first and second decode start signals, a time interval between clock pulses (T₁, T₃) contained in said first clock signal being half that between clock pulses contained in said second clock signal (T₃).
Claim 4
Dependent Claim
55 words
An information processing apparatus according to claim 2, wherein said instruction selection and hold means further includes a pointer (6) connected to said instruction selection means, for indicating a location in said buffer register of an instruction to be sent to said instruction register and update means connected to said pointer, for updating said pointer.
Claim 5
Dependent Claim
69 words
An information processing apparatus according to claim l, wherein the output of said first determination means generates in response to a first clock signal (T₁, T₃) and the output of said second determination means generates in response to a second clock signal, a time interval of clock pulses (T₁, T₃) contained in said first clock signal being half that between clock (T₂) pulses contained in said second clock signal.
References Cited (Backward Citations)
No citation records indexed.
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