EP0372190A2
Expired / Lapsed
EP
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System for accelerating execution of program instructions by a microprocessor
Assignee: Escom AG
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Filing: 1989-10-06
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Granted: —
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Expires: 2009-10-06
Abstract
Abstract A latch transfers fetched opcode to PLA for execution at the earliest opportunity following execution of a prior single cycle opcode.
Inventors
- 👤 William F. Gardei
- 👤 Jr. Charles Edward Hauck
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 02:06
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/3802; G06F9/3867; G06F9/3869
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
109 words
System for accelerating execution of program instructions by a microprocessor provided with memory, a data bus for carrying opcode fetched from memory, and a control unit for controlling and execution of opcode over one or more machine cycles, comprising: a latch for transferring fetched opcode to the control unit, a pre-decode circuit for detecting a coded bit pattern in a first opcode at the control unit and for generating a PRESYNC signal based thereon, and means for causing the latch to transfer a second fetched opcode to the control unit within one machine cycle of transfer of said first opcode to the control unit based on said PRESYNC signal.
Claim 2
Dependent Claim
109 words
System for accelerating execution of program instructions by a microprocessor provided with memory, a data bus for carrying opcode fetched from memory, and a control unit for controlling and execution of opcode over one or more machine cycles, comprising: a latch for transferring fetched opcode to the control unit, a pre-decode circuit for detecting a coded bit pattern in a first opcode at the control unit and for generating a PRESYNC signal based thereon, and means for causing the latch to transfer a second fetched opcode to the control unit within one machine cycle of transfer of said first opcode to the control unit based on said PRESYNC signal.
Claim 3
Dependent Claim
111 words
System for accelerating execution of program instructions by a microcomputer provided with memory, a data bus for carrying opcode fetched from memory, and a control unit for generating a SYNC pulse train and for controlling execution of opcode during one or more machine cycles, comprising: a latch for transferring fetched opcode to the control unit, a pre-decode circuit for detecting a coded bit pattern in a first opcode at the control unit and for generating a PRESYNC signal based thereon, means for causing the latch to transfer a second fetched opcode to the control unit during an interval between successive SYNC pulses in said pulse train based on said PRESYNC signal.
Claim 4
Dependent Claim
111 words
System for accelerating execution of program instructions by a microcomputer provided with memory, a data bus for carrying opcode fetched from memory, and a control unit for generating a SYNC pulse train and for controlling execution of opcode during one or more machine cycles, comprising: a latch for transferring fetched opcode to the control unit, a pre-decode circuit for detecting a coded bit pattern in a first opcode at the control unit and for generating a PRESYNC signal based thereon, means for causing the latch to transfer a second fetched opcode to the control unit during an interval between successive SYNC pulses in said pulse train based on said PRESYNC signal.
Claim 5
Dependent Claim
38 words
System according to any one of claims 1-2 wherein said means for causing the latch to transfer said second fetched opcode to the control unit includes means for logically combining said SYNC pulse train and said PRESYNC signal.
Claim 6
Dependent Claim
110 words
Method of accelerating execution of program instructions by a microprocessor provided with memory and a control unit for controlling execution of opcode during one or more machine cycles, comprising: coding a first opcode to indicate that the opcode can be executed within a predetermined period of time, fetching the first opcode from memory and transferring the fetched opcode to the control unit, decoding said first opcode and generating a PRESYNC signal based thereon, fetching a second opcode from memory and transferring said second opcode to the control unit within a predetermined period of time immediately following transfer of said first opcode to the control unit based on said PRESYNC signal.
Claim 7
Dependent Claim
110 words
Method of accelerating execution of program instructions by a microprocessor provided with memory and a control unit for controlling execution of opcode during one or more machine cycles, comprising: coding a first opcode to indicate that the opcode can be executed within a predetermined period of time, fetching the first opcode from memory and transferring the fetched opcode to the control unit, decoding said first opcode and generating a PRESYNC signal based thereon, fetching a second opcode from memory and transferring said second opcode to the control unit within a predetermined period of time immediately following transfer of said first opcode to the control unit based on said PRESYNC signal.
Claim 8
Dependent Claim
35 words
Method according to claim 4 including generating a SYNC pulse train and wherein said step of transferring said second opcode to the control unit includes logically combining said SYNC pulse train and said PRESYNC signal.
Claim 9
Dependent Claim
15 words
Method according to claim 4 wherein said predetermined period of time is one machine cycle.
References Cited (Backward Citations)
No citation records indexed.
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