High performance memory system

Claim 2

High performance memory system including a memory array, input circuitry connected to an input of said memory array for addressing said memory array with address information, output circuitry connected to an output of said memory array for receiving data retrieved from said memory array in response to the addressing of the memory array, and multiplexer means having an input connected to an output of said output circuitry for selecting one element of said data, characterized in that means (40a-40n) are disposed within said memory system (40) for pipelining data during the write of said data to the memory system or during the read of said data from the memory system.

Claim 3

High performance memory system, characterized in that the memory system (40) comprises a memory array (30a, 30a1), first circuit means (CKT (1)) for developing first accessing information, said first accessing information accessing said memory array for the purpose of retrieving data from said memory array; second circuit means (CKT (2)) for receiving said data retrieved from said memory array in response to the accessing performed by said first circuit means utilizing said first accessing information; first latch circuits (13) interconnected between said first circuit means and said memory array for latching said first accessing information therein; second latch circuits (15) interconnected between said second circuit means and said memory array for latching said data therein corresponding to said first accessing information, said first latch circuits latching second accessing information received from said first circuits when the second latch circuit latches said data therein corresponding to said first accessing information.

Claim 4

High performance memory system, characterized in that the memory system (40) comprises a memory array (30a, 30a1), first circuit means (CKT (1)) for developing first accessing information, said first accessing information accessing said memory array for the purpose of retrieving data from said memory array; second circuit means (CKT (2)) for receiving said data retrieved from said memory array in response to the accessing performed by said first circuit means utilizing said first accessing information; first latch circuits (13) interconnected between said first circuit means and said memory array for latching said first accessing information therein; second latch circuits (15) interconnected between said second circuit means and said memory array for latching said data therein corresponding to said first accessing information, said first latch circuits latching second accessing information received from said first circuits when the second latch circuit latches said data therein corresponding to said first accessing information.

Claim 5

High performance memory system of claim 2, wherein said first circuit means comprises: decoder circuit means (30b) for receiving information related to said first accessing information, decoding said information, and temporarily storing decoded information therein; driver circuit means (30c) connected to the first latch circuit means (40a) for receiving said decoded information and retransmitting said first accessing information in response thereto; and that the latch circuit means (40b) are interconnected between said decoder circuit means (30b) and said driver circuit means (30c) for receiving said decoded information om said decoder circuit means and latching said decoded information therein, said decoded information subsequently causing said driver circuit means to retransmit said first accessing information, said first accessing information being latched in said first latch circuit means.

Claim 6

High performance memory system of claim 3, wherein said second circuit means comprises: sensing means (30g) connected to an output of said second latch circuit means (40c) for sensing the existence of the data retrieved from said memory array (30a und 30a1) via said second latch circuit means in response to the accessing per-. formed by said first circuit means; multiplexer means (30f) for selecting one element of the data sensed by said sensing means; and fourth latch circuit means (40d) interconnected between said sensing means and said multiplexer means for latching and temporarily storing the sensed data sensed by said sensing means.

Claim 7

High performance memory system of claim 4, comprising: a plurality of further latch circuit means (40e-40h) serially connected to an input of said multiplexer means (30f) for developing an output signal, said multiplexer means selecting said one element of the sensed data in accordance with said output signal, said plurality of further latch circuit means corresponding in number to the number of latch circuit means (40a-40d) functionally involved with the accessing of said memory means and with the receipt of the data retrieved from said memory means in response to said accessing.

Claim 8

High performance memory system including a memory array, input circuitry connected to an input of said memory array for addressing said memory array with address information, output circuitry connected to an output of said memory array for receiving data retrieved from said memory array in response to the addressing of the memory array, and multiplexer means having an input connected to an output of said output circuitry for selecting one element of said data, as set forth in any of claims 2 -5 comprising: at least one first latch circuit means connected within said input circuitry for successively storing a plurality of address information, said plurality of address information successively addressing said memory array; at least one second latch circuit means connected within said output circuitry for successively storing a plurality of data, said plurality of data being successively retrieved from said memory array in response to the corresponding plurality of address information successively addressing said memory array; and a plurality of further latch circuit means serially connected to another input of said multiplexer means for storing a plurality of selection information, the plurality of selection information successively selecting a corresponding plurality of the one elements of said data.