Patent EP0128446A1 successfully refreshed from Google Patents.
← Back to Patent Explorer
EP0500151A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Microprogram control unit

Assignee: NEC Corp
•
Filing: 1986-11-10
•
Granted: —
•
Expires: 2006-11-10
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Microprogram control unit is provided for processing conditional branch micro-instructions stored in a micro-instruction memory to control the function of an information processing apparatus. Unit includes a microprogram counter coupled to the micro-instruction memory and containing address for accessing the micro-instruction stored in the memory. A circuit is provided for registering the micro-instruction received from the micro-instruction memory and having an address field coupled to the microprogram counter and a condition field for designating a condition to be judged. A detecting circuit is coupled to the registering circuits to receive the micro-instruction therefrom and for detecting the conditional branch micro-instruction. Further, there is provided a circuit for generating status signals representing respectively a plurality of the status of the information processing apparatus and selectively outputting anyone of the status signals. There is also provided a circuit for judging the coincidence between the status signal selectively outputted from the status signal generating circuit and the condition designated by the content of the condition field of the micro-instruction registered by the registering circuit to output a branch control signal. With this arrangement, the address field of the micro-program counter may be replaced by the content of the address field of the micro-instruction in accordance with the branch control signal.

Inventors

  • 👤 Hiroaki C/O Nec Corporation Kaneko

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-02 02:51
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/265

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 67 words
A microprogram control unit which includes a micro-instruction address register, comprising first means for latching at least a portion of a data, second means for extracting a portion of the data latched in the first means, third means for selectively masking a portion of the data extracted by the second means and replacing a portion of the content of the address register by the partially mask data.
Claim 2
Dependent Claim 67 words
A microprogram control unit which includes a micro-instruction address register, comprising first means for latching at least a portion of a data, second means for extracting a portion of the data latched in the first means, third means for selectively masking a portion of the data extracted by the second means and replacing a portion of the content of the address register by the partially mask data.
Claim 3
Dependent Claim 37 words
A unit as claimed in Claim 1 further including fourth means receiving a given micro-instruction so as to generate a write signal to the first means, so that the first means latches the portion of the data.
Claim 4
Dependent Claim 43 words
A unit as claimed in Claim 2 wherein the first means is a branch register coupled to a data bus and adapted to latch a portion of the data on the data bus in response to the write signal from the fourth means.
Claim 5
Dependent Claim 27 words
A unit as claimed in Claim 3 wherein the branch register is adapted to latch a less significant bit portion of the data on the data bus.
Claim 6
Dependent Claim 26 words
A unit as claimed in Claim 4, wherein the branch register is adapted to latch a least significant half of the data on the data bus.
Claim 7
Dependent Claim 26 words
A unit as claimed in Claim 4, wherein the branch register is adapted to latch a least significant half of the data on the data bus.
Claim 8
Dependent Claim 37 words
A circuit as claimed in Claim 5 wherein the second means is a muliplexer coupled to the branch register and adapted to select a portion of the data in the branch register in a given selection signal.
Claim 9
Dependent Claim 28 words
A unit as claimed in Claim 6 wherein th multiplexer operates to select either a first half or a second half of the data in the branch register.
Claim 10
Dependent Claim 36 words
A unit as claimed in Claim 6, wherein the third means is an address generator adapted to receive the output of the multiplexer and a given mask signal so as to generate a logical product therebetween.
Claim 11
Dependent Claim 43 words
A circuit as claimed in Claim 8 wherein the address generator operates to carry out a logical product between the given mask signal and a portion of the output of the muliplexer so that only the portion of the multiplexer output is masked.
Claim 12
Dependent Claim 19 words
A unit as claimed in Claim 9 wherein the address generator operates to further replace a portion of the
Claim 13
Dependent Claim 23 words
A unit as claimed in Claim 10 wherein the selection signal, the mask signal and the base signal are given by a micro-instruction.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag