Microprogram branching method and microsequencer employing the method

Claim 2

A microprogram branching method comprising the step of generating a continue address by successively incrementing an address, characterized in that there are provided the steps of: generating a branch address by referring to a branch address table (23,34) depending on predetermined branch conditions, said branch address table (23,34) prestoring branch addresses; discriminating whether or not a branch is to be made depending on the predetermined branch conditions and obtaining a discrimination result; selecting the continue address normally and selecting the branch address when the discrimination result indicates that the branch is to be made; and outputting a data which is read out from an address of a main memory (21,32) depending on the selected address, said main memory (21,32) prestoring microprograms.

Claim 3

The microprogram branching method as claimed in claim 1, characterized in that said selecting step selects the data which is read out from the main memory(21,32) and outputted depending on the discrimination result when said discriminating step discriminates certain branch conditions.

Claim 4

The microprogram branching method as claimed in claim 2, characterized in that said selecting step selects the data which is read out from the main memory (21) and outputted when a branch which is presently processed instructs an unconditional branch.

Claim 5

The microprogram branching method as claimed in any of claims 1 to 3, characterized in that said latter generating step and said discriminating step respectively use a programmable logic array.

Claim 6

The microprogram branching method as claimed in any of claims 1 to 4, characterized in that said microprogram branching method is employed in a microsequencer (30) which controls each part of a direct memory access controller by the microprograms.

Claim 7

A microsequencer adaptable to control each part of a direct memory access controller, said microsequencer comprising memory means (21, 32) for prestoring microprograms; and first generating means (22, 33a, 33b) for generating a continue address by successively incrementing an address, characterized in that there are provided: a branch address table (23, 34) which prestores branch addresses; second generating means (24, 35) for generating a branch address by referring to said branch address table depending on predetermined branch conditions; discriminating means (25, 36) for discriminating whether or not a branch is to be made depending on the predetermined branch conditions and for obtaining a discrimination result; selecting means (26, 37) for selecting the continue address normally and selecting the branch address when the discrimination result indicates that the branch is to be made; and output means (27, 38) for outputting a data which is read out from an address of said memory means depending on the address selected by said selecting means.

Claim 8

A microsequencer adaptable to control each part of a direct memory access controller, said microsequencer comprising memory means (21, 32) for prestoring microprograms; and first generating means (22, 33a, 33b) for generating a continue address by successively incrementing an address, characterized in that there are provided: a branch address table (23, 34) which prestores branch addresses; second generating means (24, 35) for generating a branch address by referring to said branch address table depending on predetermined branch conditions; discriminating means (25, 36) for discriminating whether or not a branch is to be made depending on the predetermined branch conditions and for obtaining a discrimination result; selecting means (26, 37) for selecting the continue address normally and selecting the branch address when the discrimination result indicates that the branch is to be made; and output means (27, 38) for outputting a data which is read out from an address of said memory means depending on the address selected by said selecting means.

Claim 9

The microsequencer as claimed in claim 6, characterized in that said selecting means (26, 37) selects the data which is read out from said memory means (21, 32) and outputted via said output means (27, 38) depending on the discrimination result when said discriminating means (25, 36) discriminates certain branch conditions.

Claim 10

The microsequencer as claimed in claim 7, characterized in that said selecting means (26, 37) selects the data which is read out from said memory means (21, 32) and outputted via said output means (27, 38) when a branch which is presently processed instructs an unconditional branch.

Claim 11

The microsequencer as claimed in claim any of claims 6 to 8, characterized in that said second generating means (24, 35) and said discriminating means (25, 36) are respectively made up of a programmable logic array.

Claim 12

The microsequencer as claimed in any of claims 6 to 9, characterized in that said memory means (21, 32) comprises a read only memory (32).

Claim 13

The microsequencer as claimed in any of claims 6 to 9, characterized in that said memory means (21, 32) comprises a read only memory (32) and said output means (27, 38) comprises a register (38) for storing an output data of said read only memory.