Global planarization method for inter level dielectric layers of integrated circuits

Claim 1

A method of chemical-mechanical polishing a dielectric layer comprising the steps of: a) providing a semiconductor substrate having spaced raised portions and valleys therebetween, wherein said raise portions are defined by a photolithographic process including exposing a first photoresist layer using a first optical mask; b) forming a first polish stop layer over said raised portions; c) forming a dielectric layer over said first polish stop layer; d) forming a second polish stop layer over said dielectric layer; e) forming a reduced size, reverse raised portion mask over said second polish stop layer; said reduced size reverse raised portion mask covering portions of said valleys between said raised portions, said reduced size reverse raised portion mask is in registry with said valleys, and said reduced size reverse raised portion mask has openings in registry with said raised portions; said reduced size reverse raised portion mask is a reduced size reverse image of said spaced raised portions; said reduced size reverse raise portion mask is defined by exposing a photoresist layer with said first optical mask; f) etching said second polish stop layer using said reduced size reverse raised portion mask as an etch mask leaving second polish stop blocks over said valleys; g) removing said reduced size reverse raised portion mask; and h) planarizing said dielectric layer over said raised portions using said first polish stop layer and second polish layer blocks as a polish stop thereby providing a planar surface of said dielectric layer.

Claim 2

A method of chemical-mechanical polishing a dielectric layer comprising the steps of: a) providing a semiconductor substrate having spaced raised portions and valleys therebetween, wherein said raise portions are defined by a photolithographic process including exposing a first photoresist layer using a first optical mask; b) forming a first polish stop layer over said raised portions; c) forming a dielectric layer over said first polish stop layer; d) forming a second polish stop layer over said dielectric layer; e) forming a reduced size, reverse raised portion mask over said second polish stop layer; said reduced size reverse raised portion mask covering portions of said valleys between said raised portions, said reduced size reverse raised portion mask is in registry with said valleys, and said reduced size reverse raised portion mask has openings in registry with said raised portions; said reduced size reverse raised portion mask is a reduced size reverse image of said spaced raised portions; said reduced size reverse raise portion mask is defined by exposing a photoresist layer with said first optical mask; f) etching said second polish stop layer using said reduced size reverse raised portion mask as an etch mask leaving second polish stop blocks over said valleys; g) removing said reduced size reverse raised portion mask; and h) planarizing said dielectric layer over said raised portions using said first polish stop layer and second polish layer blocks as a polish stop thereby providing a planar surface of said dielectric layer.

Claim 11

A method of chemical-mechanical polishing a dielectric layer comprising the steps of: a) providing semiconductor device structures in and on a semiconductor substrate; b) providing spaced interconnections over said semiconductor substrate; said spaced interconnections are defined by exposing a first photoresist layer using a first optical mask; c) forming an insulating layer over said interconnections forming valleys between said spaced interconnections; d) forming a first polish stop layer composed of silicon nitride over said insulating layer; e) forming a dielectric layer over said first polish stop layer; f) forming a second polish stop layer composed of silicon nitride over said dielectric layer, the combined thicknesses of said first polish stop layer, said dielectric layer and said second polish stop layer being about sufficient to fill the center of said valley coplanar with the surface of said first polish layer over said interconnects, g) forming a reduced size reverse interconnect mask over said second polish stop layer; said reduced size reverse interconnect mask is defined by photolithographic process including exposing a photoresist layer with said first optical mask; said reduce size reverse interconnect mask covering portions of said valleys between said spaced interconnection; said reduced size reverse interconnect mask is in registry with the valleys between said interconnects and said reduced size reverse interconnect mask has openings in registry with said interconnections; said reduced size reverse interconnect is reduced in area between about 1 to 4% compared to a full size reverse mask; said reduce size reverse interconnect mask has a reduce size reverse image of said spaced interconnections; etching said second polish stop layer using said reduced size reverse interconnect mask as an etch mask leaving second polish stop blocks over said valleys; and i) planarizing the resulting structure by a step of chemical-mechanical polishing said dielectric layer to remove all parts of said dielectric layer that extends above the surface of said first polish stop over said interconnections and the coplanar surface of said second polish blocks layer over the center of said valley, whereby said second polish stops blocks prevent dishing of said dielectric layer.

Claim 12

A method of chemical-mechanical polishing a dielectric layer comprising the steps of: a) providing semiconductor device structures in and on a semiconductor substrate; b) providing spaced interconnections over said semiconductor substrate; said spaced interconnections are defined by exposing a first photoresist layer using a first optical mask; c) forming an insulating layer over said interconnections forming valleys between said spaced interconnections; d) forming a first polish stop layer composed of silicon nitride over said insulating layer; e) forming a dielectric layer over said first polish stop layer; f) forming a second polish stop layer composed of silicon nitride over said dielectric layer, the combined thicknesses of said first polish stop layer, said dielectric layer and said second polish stop layer being about sufficient to fill the center of said valley coplanar with the surface of said first polish layer over said interconnects, g) forming a reduced size reverse interconnect mask over said second polish stop layer; said reduced size reverse interconnect mask is defined by photolithographic process including exposing a photoresist layer with said first optical mask; said reduce size reverse interconnect mask covering portions of said valleys between said spaced interconnection; said reduced size reverse interconnect mask is in registry with the valleys between said interconnects and said reduced size reverse interconnect mask has openings in registry with said interconnections; said reduced size reverse interconnect is reduced in area between about 1 to 4% compared to a full size reverse mask; said reduce size reverse interconnect mask has a reduce size reverse image of said spaced interconnections; etching said second polish stop layer using said reduced size reverse interconnect mask as an etch mask leaving second polish stop blocks over said valleys; and i) planarizing the resulting structure by a step of chemical-mechanical polishing said dielectric layer to remove all parts of said dielectric layer that extends above the surface of said first polish stop over said interconnections and the coplanar surface of said second polish blocks layer over the center of said valley, whereby said second polish stops blocks prevent dishing of said dielectric layer.

Claim 18

A method of chemical-mechanical polishing a dielectric layer comprising the steps of: a) providing semiconductor device structures in and on a semiconductor substrate; b) providing spaced interconnections over said semiconductor substrate; said spaced interconnections defined using a first optical mask; c) forming an insulating layer over said interconnections forming valleys between said spaced interconnections; said spaced interconnections have a height in a range of between about 3000 and 10,000 Å and a width in a range of between about 1 and 300 μm and a first spacing between said interconnections in a range of between about 1 and 300 μM; d) forming a first polish stop layer composed of silicon nitride over said insulating layer; e) forming a dielectric layer over said first polish stop layer; said dielectric layer is composed of silicon oxide and said dielectric layer having thickness in a range of between about 10,000 and 30,000 Å; f) forming a second polish stop layer composed of silicon nitride over said dielectric layer, the combined thicknesses of said first polish stop layer, said dielectric layer and said second polish stop layer being about sufficient to fill the center of said valley coplanar with the surface of said first polish layer over said interconnects; said second polish stop layer is composed of silicon nitride and said second polish layer having a thickness in a range of between about 100 and 2000 Å; g) forming a reduced size reverse interconnect mask over said second polish stop layer; said reduced size reverse interconnect mask covering portions of said valleys between said spaced interconnections; said reduced size reverse interconnect mask is in registry with said valleys between said interconnects, and said reduced size reverse interconnect mask has openings in registry with the interconnections; said reduced size reverse interconnect mask is reduced in area between about 1 to 4% compared to a full size reverse mask; said reduced size reverse interconnect mask is a reduced size reverse image of said spaced interconnects said reduced size reverse interconnect mask is defined by a photolithographic process including exposing a photoresist layer with said first optical mask; h) etching said second polish stop layer using said reduced size reverse interconnect mask as an etch mask leaving second polish stop blocks over said valleys; i) planarizing the resulting structure by a step of chemical-mechanical polishing said dielectric layer to remove all parts of said dielectric layer that extends above the surface of said first polish stop over said interconnects and the coplanar surface of said second polish blocks layer over the center of said valley, whereby said second polish stops blocks prevent dishing of said dielectric layer.

Claim 19

A method of chemical-mechanical polishing a dielectric layer comprising the steps of: a) providing semiconductor device structures in and on a semiconductor substrate; b) providing spaced interconnections over said semiconductor substrate; said spaced interconnections defined using a first optical mask; c) forming an insulating layer over said interconnections forming valleys between said spaced interconnections; said spaced interconnections have a height in a range of between about 3000 and 10,000 Å and a width in a range of between about 1 and 300 μm and a first spacing between said interconnections in a range of between about 1 and 300 μM; d) forming a first polish stop layer composed of silicon nitride over said insulating layer; e) forming a dielectric layer over said first polish stop layer; said dielectric layer is composed of silicon oxide and said dielectric layer having thickness in a range of between about 10,000 and 30,000 Å; f) forming a second polish stop layer composed of silicon nitride over said dielectric layer, the combined thicknesses of said first polish stop layer, said dielectric layer and said second polish stop layer being about sufficient to fill the center of said valley coplanar with the surface of said first polish layer over said interconnects; said second polish stop layer is composed of silicon nitride and said second polish layer having a thickness in a range of between about 100 and 2000 Å; g) forming a reduced size reverse interconnect mask over said second polish stop layer; said reduced size reverse interconnect mask covering portions of said valleys between said spaced interconnections; said reduced size reverse interconnect mask is in registry with said valleys between said interconnects, and said reduced size reverse interconnect mask has openings in registry with the interconnections; said reduced size reverse interconnect mask is reduced in area between about 1 to 4% compared to a full size reverse mask; said reduced size reverse interconnect mask is a reduced size reverse image of said spaced interconnects said reduced size reverse interconnect mask is defined by a photolithographic process including exposing a photoresist layer with said first optical mask; h) etching said second polish stop layer using said reduced size reverse interconnect mask as an etch mask leaving second polish stop blocks over said valleys; i) planarizing the resulting structure by a step of chemical-mechanical polishing said dielectric layer to remove all parts of said dielectric layer that extends above the surface of said first polish stop over said interconnects and the coplanar surface of said second polish blocks layer over the center of said valley, whereby said second polish stops blocks prevent dishing of said dielectric layer.