EP0545263A2
Expired / Lapsed
EP
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Method of forming trench isolation having polishing step and method of manufacturing semiconductor device
Assignee: Sony Corp
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Filing: 1992-11-25
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Granted: —
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Expires: 2012-11-25
Abstract
Abstract A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing is conducted by disposing an isotropic etching step, a multi-layered etching stopper and a protrusion unifying structure. Polishing can be attained with satisfactory flatness uniformly or with no polishing residue even in a portion to be polished in which the etching stopper layer is distributed unevenly. The method can be applied to manufacture of a semiconductor device or the like.
Inventors
- 👤 Tetsuo Gocho
- 👤 Hideaki Hayakawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 10:24
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/668; H10P14/6681; H10P14/6684; H10P14/6686; H10P50/00; H10P50/20; H10P50/24; H10P50/242; H10P50/28; H10P50/282; H10P50/283; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17; H10P14/694; H10P14/6943; H10P14/69433; Y; Y10; Y10S; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
54 words
A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing, wherein the method comprises at least an isotropic etching step for isotropically etching the burying material before the polishing step.
Claim 2
Dependent Claim
117 words
A method of forming trench isolation as defined in claim 1, wherein trenches are formed in a structure which has an etching stopper layer comprising a three-layered structure, and in which the upper layer of said etching stopper layer comprises a film having a polishing rate smaller than that of the burying material and an etching rate also smaller than that of the burying material, an intermediate layer of said etching stopper layer comprises a film having an etching rate smaller than that of the upper layer and a lower layer of said etching stopper layer comprises a film having an etching rate smaller than that of the intermediate layer and greater than that of the substrate.
Claim 3
Dependent Claim
24 words
A method of manufacturing a semiconductor device of forming trench isolation by using the method of forming trench isolation as defined in claim 1.
Claim 4
Dependent Claim
24 words
A method of manufacturing a semiconductor device of forming trench isolation by using the method of forming trench isolation as defined in claim 2.
Claim 5
Independent Claim
55 words
A method of manufacturing a semiconductor device for forming trench isolation, which comprises a burying step of burying trenches by a bias ECR-CVD process, an isotropic etching step of isotropically etching a burying material thereby etching the burying material on a wide protrusion region and a polishing step of flattening the burying material by polishing.
Claim 6
Independent Claim
71 words
A method of manufacturing a semiconductor device for forming trench isolation by forming trenches in a structure, in which a substrate to form trench isolation has an etching stopper layer comprising a three-layered structure, in which the upper layer of said etching stopper layer comprises silicon nitride, an intermediate layer of said etching stopper layer comprises polysilicon and a lower layer of said etching stopper layer comprises a silicon dioxide film.
Claim 7
Independent Claim
87 words
A method of manufacturing a semiconductor device having a polishing step including a step of burying recesses defined with a plurality of protrusion patterns by a burying material and a polishing step of flattening the burying material formed on the protrusion patterns by polishing, which comprises previously forming a pattern that constitutes a stopper layer for polishing and that is not intended directly for the function as a wiring or insulation portion, to a portion in which the density of the stopper layer for polishing is coarse.
Claim 8
Dependent Claim
52 words
A method of manufacturing a semiconductor device having a polishing step as defined in claim 7. wherein the patterns by polishing, which comprises previously forming a pattern that constitutes a stopper layer for polishing and that is not intended directly for the function as a wiring or insulation portion is finally removed.
Claim 9
Independent Claim
123 words
A method of manufacturing a semiconductor device having a polishing step including a step of burying recesses defined with a plurality of protrusion patterns with a burying material on a semiconductor substrate having said plurality of protrusion patterns comprising a wide protrusion regions and narrow protrusion regions, and a step of flattening the burying material formed on the protrusion patterns by polishing, wherein the method comprises a step of previously forming a pattern that constitutes a stopper layer for polishing and that is finally removed to a portion in which the density of the stopper layer for polishing is coarse, and a step of at least partially etching the burying material on the wide protrusion regions prior to the flattening step by polishing.
Claim 10
Independent Claim
108 words
A method of manufacturing a semiconductor device in which a plurality of protrusion patterns are formed on a substrate and trenches comprising recesses defined there-between are buried, wherein a pattern as a stopper layer for polishing is previously formed to a portion in which the density of the protrusion patterns formed with the stopper layer for polishing is coarse to obtain a structure having the protrusions being uniformly distributed, thereby making the area ratio of the stopper layer uniform, subsequently, a burying material is deposited and then the burying material on the protrusion patterns and said previously formed patterns are removed by polishing to obtain a flattened structure.
Claim 11
Independent Claim
34 words
A method of manufacturing a semiconductor device as defined in any one of claims 7 to 10, wherein the burying material is silicon dioxide and the layer as the polishing stopper comprises silicon nitride.
Claim 12
Independent Claim
38 words
A method of manufacturing a semiconductor device as defined in any one of claims 7 to 11, wherein the burying material is silicon dioxide and a bias ECR-CVD process is used for the formation of the burying material.
Claim 13
Independent Claim
39 words
A method of manufacturing a semiconductor device as defined in any one of claims 7 to 11, wherein the burying material is silicon dioxide and an atmospheric pressure CVD process is used for the formation of the burying material.
Claim 14
Dependent Claim
24 words
A method of manufacturing a semiconductor device as defined in claim 13, wherein CVD silicon dioxide is formed by using an organic silicon gas.
Claim 15
Dependent Claim
63 words
A method of manufacturing a semiconductor device as defined in claim 9, wherein the layer constituting the polishing stopper comprises silicon nitride and a step of at least partially removing the burying material on the wide protrusion region prior to the flattening step by polishing utilizes a means of applying isotropic etching while masking other positions than the etched portion with a resist.
Claim 16
Independent Claim
114 words
A method of manufacturing a semiconductor device including a burying step for forming a recess burying material by a deposition means on a substrate formed with a plurality of recesses and a polishing step of flattening the burying material by polishing, wherein the method comprises a resist forming step of forming a resist on the substrate after the polishing step, a resist pattern forming step of forming a resist pattern while exposing the burying material remaining in the portions other than the recesses to be buried, and a removing step of removing the burying material remaining in the portions other than the recesses to be buried by using the resist pattern as a mask.
Claim 17
Independent Claim
83 words
A method of manufacturing a semiconductor device including a burying step for forming recess burying material by a deposition means on a substrate formed with a plurality of recesses and a polishing step of flattening the burying material by polishing, wherein the method comprises a flattened layer forming step of forming a flattened layer on the substrate, and an etching back step for etching back under the condition in which an etching rate is equal between the flattened layer and the burying material.
Claim 18
Independent Claim
147 words
A method of manufacturing a semiconductor device which comprises burying silicon dioxide as a burying material into a plurality of recesses on a substrate having a silicon nitride film as a stopper layer for polishing by a base CR-CVD process and then conducting a polishing step of flattening the burying material by polishing, conducting a resist forming step of forming a resist on a substrate after the polishing step and a resist pattern forming step of forming a resist pattern while exposing the burying material remaining in the portion other than recesses to be buried as the burying material not removed completely and, subsequently, conducting a removing step of removing the burying material remaining in the portion other than the recesses to be buried by using the resist pattern as a mask, thereby conducting burying and flattening with no residue of the burying material not removed completely.
Claim 19
Independent Claim
108 words
A method of manufacturing a semiconductor device which comprises: a burying step of forming a recess burying material by depositing silicon dioxide by a bias ECR-CVD process on a substrate in which a plurality of recesses are formed and a silicon nitride film is formed as a stopper layer for polishing stopper, a polishing step of flattening the burying material by polishing, a flattened layer forming step of forming a flattened layer on a substrate by a resist or SOG and an etching back step of applying etching back in a condition in which an etching rate is made equal between the flattened layer and the burying material.
Claim 20
Independent Claim
84 words
A method of manufacturing a semiconductor device having a polishing step including a step of forming a plurality of protrusion patterns each having a stopper layer for polishing in the upper portion, a step of burying recesses defined with a plurality of protrusion patterns by a burying material and a step of flattening the burying material formed on the protrusion patterns by polishing, wherein the method comprises forming a second polishing stopper layer at least on the recess burying material after burying the recesses.
Claim 21
Independent Claim
94 words
A method of manufacturing a semiconductor device including a step of forming a plurality of protrusion patterns each having a stopper layer for polishing in the upper portion, a step of burying a plurality of recesses comprising wide recesses and narrow recesses defined with a plurality of protrusion patterns by a burying material and a step of flattening the burying material formed on the protrusion patterns by polishing, wherein the method comprises forming a second stopper layer for polishing at least on the entire surface of the recess burying material after burying the recesses.
Claim 22
Independent Claim
132 words
A method of manufacturing a semiconductor device which comprises forming a plurality of protrusion patterns on a substrate having a silicon nitride layer as a stopper layer for polishing and a poly-Si layer as an etching stopper layer of the silicon nitride layer in the upper portion, forming silicon dioxide as a burying material in recesses defined with a plurality of protrusion patterns by a CVD process, burying the recesses, subsequently, forming a second stopper layer for polishing over the entire surface, leaving a second stopper layer for polishing only on the burying material in a wide recess in a portion in which the density of the stopper layer for polishing is coarse by an etching step using a resist, and, thereafter, flattening the burying material formed on the recesses by polishing.
Claim 23
Dependent Claim
26 words
A method of manufacturing a semiconductor device as defined in claim 22, wherein silicon dioxide as the burying material is formed by a O₃-TEOS CVD process.
Claim 24
Independent Claim
33 words
A method of manufacturing a semiconductor device as defined in any one of claims 20 to 23, wherein the burying material and the stopper layer for polishing are formed by a CVD process.
Claim 25
Independent Claim
39 words
A method of manufacturing a semiconductor device as defined in any one of claims 20 to 23, wherein the burying material and the stopper layer for polishing are formed by a deposition means for applying etching and deposition simultaneously.
Claim 26
Dependent Claim
27 words
A method of manufacturing a semiconductor device as defined in claim 25, wherein the deposition means for applying etching and deposition simultaneously is a bias ECR-CVD process.
Claim 27
Dependent Claim
33 words
A method of manufacturing a semiconductor device as defined in claim 25 or 26, wherein the second stopper layer for polishing is formed over the entire surface of the recesses that constitute trenches.
References Cited (Backward Citations)
No citation records indexed.
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