Method for fabricating semiconductor device with planarization step using CMP

Claim 1

A method for fabricating a semiconductor device comprising the steps of: forming, by one of atmospheric pressure CVD and low pressure CVD without using plasma, a first insulating layer that covers a semiconductor substrate; forming, by bias plasma CVD using an electron cyclotron resonance process, a second insulating film that covers said first insulating layer; and planarizing said second insulating film by a CMP process.

Claim 2

A method for fabricating a semiconductor device comprising the steps of: forming, by one of atmospheric pressure CVD and low pressure CVD without using plasma, a first insulating layer that covers a semiconductor substrate; forming, by bias plasma CVD using an electron cyclotron resonance process, a second insulating film that covers said first insulating layer; and planarizing said second insulating film by a CMP process.

Claim 3

A method for fabricating a semiconductor device comprising the steps of: forming a first MOS transistor having a first gate electrode formed as a protrusion at a first region on a semiconductor substrate; forming a second MOS transistor having a second gate electrode formed as a protrusion at a second region on said semiconductor substrate; forming a first insulating film provided between said first region and said second region for isolating said first MOS transistor and said second MOS transistor from each other; forming, by one of atmospheric pressure CVD and low pressure CVD without using plasma, a second insulating film covering said first region and said second region as well as said semiconductor substrate; forming, by a bias plasma CVD using an electron cyclotron resonance process, a third insulating film that covers said second insulating layer; and planarizing said third insulating film by a CMP process.

Claim 4

A method for fabricating a semiconductor device comprising the steps of: forming a first MOS transistor having a first gate electrode formed as a protrusion at a first region on a semiconductor substrate; forming a second MOS transistor having a second gate electrode formed as a protrusion at a second region on said semiconductor substrate; forming a first insulating film provided between said first region and said second region for isolating said first MOS transistor and said second MOS transistor from each other; forming, by one of atmospheric pressure CVD and low pressure CVD without using plasma, a second insulating film covering said first region and said second region as well as said semiconductor substrate; forming, by a bias plasma CVD using an electron cyclotron resonance process, a third insulating film that covers said second insulating layer; and planarizing said third insulating film by a CMP process.

Claim 7

A method for fabricating a semiconductor device comprising the steps of: forming, by one of atmospheric pressure CVD and low pressure CVD without using plasma, a first insulating layer that covers a semiconductor substrate having a surface from which a plurality of gate electrodes and an element isolation region protrude; forming, by bias plasma CVD using an electron cyclotron resonance process, a second insulating film that covers said first insulating layer, wherein said second insulating film has a surface on which a plurality of small protrusions are formed, and wherein a width of said plurality of small protrusions above said surface of said second insulating film is narrower than a width of protrusions formed by said plurality of gate electrodes and said element isolation region disposed on said semiconductor substrate and covered by said first insulating layer; and planarizing said plurality of small protrusions formed on said second insulating film by a CMP process.

Claim 8

A method for fabricating a semiconductor device comprising the steps of: forming, by one of atmospheric pressure CVD and low pressure CVD without using plasma, a first insulating layer that covers a semiconductor substrate having a surface from which a plurality of gate electrodes and an element isolation region protrude; forming, by bias plasma CVD using an electron cyclotron resonance process, a second insulating film that covers said first insulating layer, wherein said second insulating film has a surface on which a plurality of small protrusions are formed, and wherein a width of said plurality of small protrusions above said surface of said second insulating film is narrower than a width of protrusions formed by said plurality of gate electrodes and said element isolation region disposed on said semiconductor substrate and covered by said first insulating layer; and planarizing said plurality of small protrusions formed on said second insulating film by a CMP process.