US5602056A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming reliable MOS devices using silicon rich plasma oxide film
Assignee: NXP BV
•
Filing: 1995-05-04
•
Granted: 1997-02-11
•
Expires: 2015-05-04
Abstract
Abstract The invention relates to MOS devices and methods for fabricating MOS devices having multilayer metallization. In accordance with preferred embodiments, internal passivation is used for suppressing device degradation from internal sources. Preferred devices and methods for fabricating such devices include formation of one or more oxide layers which are enriched with silicon to provide such an internal passivation and improve hot carrier lifetime. Preferred methods for fabricating MOS devices having multi-level metallization include modifying the composition of a PECVD oxide film and, in some embodiments, the location and thickness of such an oxide. In an exemplary preferred embodiment, PECVD oxide layers are modified by changing a composition to a silicon enriched oxide.
Inventors
- 👤 Vivek Jain
- 👤 Dipankar Pramanik
- 👤 Subhash R. Nariani
- 👤 Kuang-Yeh Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:02
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/6342; H10P14/66; H10P14/662; H10P14/668; H10P14/6681; H10P14/6682; H10P14/6684; H10P14/6686; H10P14/69215; H10P14/6923; H10P14/694; H10P14/6943; H10P14/69433; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10W74/00; H10W74/40; H10W74/43; H10W74/481; H10B; H10B69/00
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
86 words
A method of making an integrated circuit comprising the steps of: forming a plurality of electrical devices having gates on a substrate; forming an isolation layer between said electrical devices for electrically isolating the electrical devices; forming a first silicon-enriched oxide layer on said isolation layer and gates of said electrical devices; providing a first metallization layer above said first silicon-enriched oxide layer; providing a second silicon-enriched oxide layer on said first metallization layer; and providing a second metallization layer above said second silicon-enriched oxide layer.
Claim 2
Independent Claim
86 words
A method of making an integrated circuit comprising the steps of: forming a plurality of electrical devices having gates on a substrate; forming an isolation layer between said electrical devices for electrically isolating the electrical devices; forming a first silicon-enriched oxide layer on said isolation layer and gates of said electrical devices; providing a first metallization layer above said first silicon-enriched oxide layer; providing a second silicon-enriched oxide layer on said first metallization layer; and providing a second metallization layer above said second silicon-enriched oxide layer.
Claim 3
Dependent Claim
56 words
The method of making an integrated circuit according to claim 1 further comprising the steps of: forming a planarization layer on said second silicon-enriched oxide layer; forming a third enriched silicon oxide layer; providing said second metallization layer on said third silicon-enriched oxide layer; and forming at least one passivation layer on said second metallization layer.
Claim 4
Dependent Claim
20 words
The method of making an integrated circuit according to claim 2, further comprising the step of: etching said planarization layer.
Claim 5
Dependent Claim
43 words
A method of making an integrated circuit according to claim 1, wherein said step of forming said first silicon-enriched oxide layer further includes the step of: forming said silicon-enriched oxide layer in contact with said isolation layer and gates of said electrical devices.
Claim 6
Independent Claim
113 words
A method of making an integrated circuit having improved hot carrier reliability comprising the steps of: forming an isolation means for isolating devices on a substrate; forming a gate oxide layer on a substrate; forming a gate on the gate oxide layer; forming a first silicon-enriched oxide layer on said isolation means, in contact with said gate; and forming a dielectric layer on said first silicon-enriched oxide layer; forming a metallization layer on a side of said dielectric layer which is opposite said first silicon-enriched oxide layer, said first silicon-enriched oxide layer being formed in a location which inhibits fabrication of said metallization layer from affecting electron carrying characteristics of said gate oxide.
Claim 7
Independent Claim
113 words
A method of making an integrated circuit having improved hot carrier reliability comprising the steps of: forming an isolation means for isolating devices on a substrate; forming a gate oxide layer on a substrate; forming a gate on the gate oxide layer; forming a first silicon-enriched oxide layer on said isolation means, in contact with said gate; and forming a dielectric layer on said first silicon-enriched oxide layer; forming a metallization layer on a side of said dielectric layer which is opposite said first silicon-enriched oxide layer, said first silicon-enriched oxide layer being formed in a location which inhibits fabrication of said metallization layer from affecting electron carrying characteristics of said gate oxide.
Claim 8
Dependent Claim
25 words
The method of making an integrated circuit according to claim 5, further comprising the step: providing a second silicon-enriched oxide layer on said metallization layer.
Claim 9
Dependent Claim
56 words
The method of making an integrated circuit according to claim 6 further comprising the steps of: forming a planarization layer on said second silicon-enriched oxide layer; forming a third enriched silicon oxide layer; providing a second metallization layer on said third silicon-enriched oxide layer; and forming at least one passivation layer on said second metallization layer.
Claim 10
Dependent Claim
20 words
The method of making an integrated circuit according to claim 7, further comprising the step of: etching said planarization layer.
Claim 11
Dependent Claim
20 words
The method of making an integrated circuit according to claim 5, wherein said isolation means is a field oxide layer.
Claim 12
Independent Claim
81 words
A method of making an integrated circuit with improved electrical reliability, said method comprising the steps of: forming at least one electrical device on a substrate, with a first side of said electrical device being in contact with said substrate; and forming a protective layer of silicon-enriched oxide on a second side of said electrical device, said second side being opposite said first side, for protecting said electrical device from electrical degradation during fabrication subsequent to formation of the protective layer.
Claim 13
Independent Claim
81 words
A method of making an integrated circuit with improved electrical reliability, said method comprising the steps of: forming at least one electrical device on a substrate, with a first side of said electrical device being in contact with said substrate; and forming a protective layer of silicon-enriched oxide on a second side of said electrical device, said second side being opposite said first side, for protecting said electrical device from electrical degradation during fabrication subsequent to formation of the protective layer.
Claim 14
Dependent Claim
37 words
The method of making an integrated circuit according to claim 10, said method further comprising the step of: forming a first metallization layer above said at least one electrical device subsequent to formation of said silicon-enriched oxide.
Claim 15
Dependent Claim
46 words
The method of making an integrated circuit according to claim 11, said method further comprising the step of: forming a second silicon-enriched oxide layer subsequent to formation of said first metallization layer, said second silicon-enriched oxide layer being formed in contact with said first metallization layer.
Claim 16
Dependent Claim
48 words
The method of making an integrated circuit according to claim 12, said method further comprising the steps of: forming a third silicon-enriched oxide layer subsequent to formation of said second silicon-enriched oxide layer; and forming a second metallization layer subsequent to formation of said third silicon-enriched oxide layer.
References Cited (Backward Citations)
US3649884A
Cited
US4123565A
Cited
US4375125A
Cited
US4688078A
Cited
US4502202A
Cited
US4613888A
Cited
US4555300A
Cited
US4732801A
Cited
US4810673A
Cited
US5047829A
Cited
US4972250A
Cited
US5110766A
Cited
US5057897A
Cited
US5128279A
Cited
US5290727A
Cited
US4996167A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |