US5717254A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device including a plurality of transistors
Assignee: Fujitsu Semiconductor Ltd
•
Filing: 1994-09-13
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Granted: 1998-02-10
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Expires: 2014-09-13
Abstract
Abstract A semiconductor device of the present invention includes an insulating layer covering a plurality of semiconductor elements formed in a semiconductor layer, an opening portion formed in the insulating layer respective conductive porions of the plurality of semiconductor elements in the insulating layer, and a conductive pattern formed in the opening portion for connecting respective conductive portions of the plurality of semiconductor elements.
Inventors
- 👤 Koichi Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:30
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
234 words
A semiconductor device comprising: a first insulating layer formed on a part of a semiconductor substrate; a plurality of transistors including a first transistor and a second transistor formed in said semiconductor substrate in regions surrounded by said first insulating layer, each of said transistors having a gate electrode extending on said first insulating layer and impurity diffused layers on both sides of gate electrode; a second insulating layer covering said transistors and said gate electrodes on said first insulating layer; a first opening portion formed in said second insulating layer, said first opening portion exposing one of said impurity diffused layers of said first transistor and one of said gate electrodes; a second opening portion formed in said second insulating layer, said second opening portion exposing one of said impurity diffused layers of said second transistor and said one of said gate electrodes; a first conductive pattern burying said first opening for contacting said impurity diffused layer of said first transistor and said one of said gate electrodes in said first opening portion, said first conductive pattern is separated from other transistors of said plurality of transistors; and a second conductive pattern burying said second opening for contacting said impurity diffused layer of said second transistor and said one of said gate electrodes in said second opening portion, said second conductive pattern is separated from the other transistors of said plurality of transistors.
Claim 2
Dependent Claim
234 words
A semiconductor device comprising: a first insulating layer formed on a part of a semiconductor substrate; a plurality of transistors including a first transistor and a second transistor formed in said semiconductor substrate in regions surrounded by said first insulating layer, each of said transistors having a gate electrode extending on said first insulating layer and impurity diffused layers on both sides of gate electrode; a second insulating layer covering said transistors and said gate electrodes on said first insulating layer; a first opening portion formed in said second insulating layer, said first opening portion exposing one of said impurity diffused layers of said first transistor and one of said gate electrodes; a second opening portion formed in said second insulating layer, said second opening portion exposing one of said impurity diffused layers of said second transistor and said one of said gate electrodes; a first conductive pattern burying said first opening for contacting said impurity diffused layer of said first transistor and said one of said gate electrodes in said first opening portion, said first conductive pattern is separated from other transistors of said plurality of transistors; and a second conductive pattern burying said second opening for contacting said impurity diffused layer of said second transistor and said one of said gate electrodes in said second opening portion, said second conductive pattern is separated from the other transistors of said plurality of transistors.
Claim 3
Dependent Claim
30 words
The semiconductor device according to claim 1, wherein a conductive layer is formed in a self-aligned manner on a surface of the impurity diffused layers constituting said plurality of transistors.
Claim 4
Dependent Claim
25 words
The semiconductor device according to claim 2, wherein said conductive layer formed in the self-aligned manner is a silicide layer formed by a salicide technique.
Claim 5
Dependent Claim
19 words
The semiconductor device according to claim 1, wherein said gate electrodes of said plurality of transistors contain tungsten silicide.
Claim 6
Dependent Claim
26 words
The semiconductor device according to claim 1, wherein a conductive layer is formed in a self-aligned manner above said gate electrodes of said plurality of transistors.
Claim 7
Dependent Claim
20 words
The semiconductor device according to claim 5, wherein said conductive layer is a silicide layer formed by a salicide technique.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-02-09 | 2001-08-11 | 2002-02-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-02-09 | 2005-08-11 | 2006-02-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-02-09 | 2009-08-11 | 2010-02-10 | $7700.00 | Window Closed / Lapsed |