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US5699551A
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Software invalidation in a multiple level, multiple cache system
Assignee: ARM Finance Overseas Ltd
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Filing: 1995-06-07
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Granted: 1997-12-16
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Expires: 2015-06-07
Abstract
Abstract A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a bit indicative of the validity of the line. The method provides a software invalidate instruction which bypasses any address translation mechanism. Included in the software invalidate instruction is a first field to identify within which multiple cache the line is to be avoided. A target address is generated to index each level of the cache memory system. The state of the bit is changed in accordance with the address and the invalidate instruction.
Inventors
- 👤 George S. Taylor
- 👤 P. Michael Farmwald
- 👤 Timothy P. Layman
- 👤 Huy Xuan Ngo
- 👤 Allen W. Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:26
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0891; G06F12/0888; G06F12/0893; G06F12/0897; G06F12/10; G06F12/1027; G06F12/1045
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
116 words
A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache system, wherein each line of the multiple level, multiple cache system includes a tag field, a data field, and a bit indicative of the validity of the line, the method comprising: providing a software invalidate instruction which bypasses any address translation mechanism; including in the invalidate instruction a first field to identify within which multiple cache the line is to be avoided; generating a target address to index each level of the cache system; and in response to the address and the invalidate instruction changing the state of the bit to thereby mark the line as invalid.
Claim 2
Independent Claim
116 words
A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache system, wherein each line of the multiple level, multiple cache system includes a tag field, a data field, and a bit indicative of the validity of the line, the method comprising: providing a software invalidate instruction which bypasses any address translation mechanism; including in the invalidate instruction a first field to identify within which multiple cache the line is to be avoided; generating a target address to index each level of the cache system; and in response to the address and the invalidate instruction changing the state of the bit to thereby mark the line as invalid.
Claim 3
Independent Claim
113 words
A method of invalidating a line in a designated cache of a cache system, wherein the cache system is designed to provide access to the data in a random access memory, the method comprising the steps of: maintaining a bit indicative of the validity of the line; modifying the value of the bit according to accesses to the memory locations in the random access memory, wherein the accesses specify an address of the memory locations; providing an invalidate instruction having a field to identify the line; identifying the line according to the field; and changing the state of the bit in response to the invalidate instruction to thereby mark the line as invalid.
Claim 4
Independent Claim
113 words
A method of invalidating a line in a designated cache of a cache system, wherein the cache system is designed to provide access to the data in a random access memory, the method comprising the steps of: maintaining a bit indicative of the validity of the line; modifying the value of the bit according to accesses to the memory locations in the random access memory, wherein the accesses specify an address of the memory locations; providing an invalidate instruction having a field to identify the line; identifying the line according to the field; and changing the state of the bit in response to the invalidate instruction to thereby mark the line as invalid.
Claim 5
Independent Claim
25 words
The method of step 2, wherein the invalidate instruction does not specify an address of any of the memory locations of the random access memory.
Claim 6
Independent Claim
25 words
The method of step 2, wherein the invalidate instruction does not specify an address of any of the memory locations of the random access memory.
Claim 7
Dependent Claim
34 words
The method of claim 3, wherein the cache system comprises a multiple level and wherein the step of identifying the line comprises generating a target address to index each level of the cache system.
Claim 8
Dependent Claim
22 words
The method of claim 4, wherein the step of providing an invalidate instruction comprises the further step of providing a software instruction.
Claim 9
Dependent Claim
22 words
The method of claim 2, wherein the step of providing an invalidate instruction comprises the further step of providing a software instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-12-15 | 2001-06-16 | 2001-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-12-15 | 2005-06-16 | 2005-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-12-15 | 2009-06-16 | 2009-12-16 | $7700.00 | Window Closed / Lapsed |