US5058006A
Expired / Lapsed
US
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Method and apparatus for filtering invalidate requests
Assignee: Hewlett Packard Development Co LP
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Filing: 1988-06-27
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Granted: 1991-10-15
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Expires: 2008-06-27
Abstract
Abstract An apparatus which filters the number of invalidates to be propagated onto a private processor bus is provided. This is desirable so that the processor bus is not overloaded with invalidate requests. The present invention describes a method of filtering the number of invalidates to be propagated to each processor. A memory interface filters the invalidates by using a second private bus, the invalidate bus, which communicates with the cache controller. The cache controller can tell the memory interface whether data corresponding to the address on the invalidate bus is resident in the private cache memory of that processor. In this way, the memory interface only has to request the private processor bus when necessary, in order to perform the invalidate.
Inventors
- 👤 W. Hugh Durdan
- 👤 Rebecca L. Stamm
- 👤 G. Michael Uhler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:25
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0808
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
305 words
A method of operating a computer system, the computer system having a main memory for storing blocks of data, said compute system further having a plurality of processors capable of issuing write transactions defining invalidate requests, said computer system further having a system bus for intercoupling said main memory and said processors, each of said processors having an associated primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for identifying blocks of memory addresses resident in said primary cache memory, each of said processors further having a memory interface for detecting write transactions on said system bus, each of said processors further having a cache controller coupled to said memory interface by an invalidate bus, said cache controller including a secondary cache memory for storing a subset of the data stored in said main memory and a secondary cache tag store for identifying blocks of memory addresses resident in said secondary cache memory, said cache controller further including a copy of the primary cache tag store, said method of operating including filtering invalidate requests by the steps of: a. detecting a write transaction on the system bus by a memory interface, said write transaction defining a memory location in said main memory; b. forwarding the memory address so defined by the memory interface to the cache controller by way of said invalidate bus; c. comparing said memory address to memory addresses indicated in said secondary cache tag store and in said copy of the primary cache tag store; and d. if said memory address is indicated in either said secondary cache tag store or said copy of the primary cache tag store, issuing an invalidate request on said processor bus, otherwise ignoring said write transaction by the memory interface detecting the write transaction.
Claim 2
Independent Claim
305 words
A method of operating a computer system, the computer system having a main memory for storing blocks of data, said compute system further having a plurality of processors capable of issuing write transactions defining invalidate requests, said computer system further having a system bus for intercoupling said main memory and said processors, each of said processors having an associated primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for identifying blocks of memory addresses resident in said primary cache memory, each of said processors further having a memory interface for detecting write transactions on said system bus, each of said processors further having a cache controller coupled to said memory interface by an invalidate bus, said cache controller including a secondary cache memory for storing a subset of the data stored in said main memory and a secondary cache tag store for identifying blocks of memory addresses resident in said secondary cache memory, said cache controller further including a copy of the primary cache tag store, said method of operating including filtering invalidate requests by the steps of: a. detecting a write transaction on the system bus by a memory interface, said write transaction defining a memory location in said main memory; b. forwarding the memory address so defined by the memory interface to the cache controller by way of said invalidate bus; c. comparing said memory address to memory addresses indicated in said secondary cache tag store and in said copy of the primary cache tag store; and d. if said memory address is indicated in either said secondary cache tag store or said copy of the primary cache tag store, issuing an invalidate request on said processor bus, otherwise ignoring said write transaction by the memory interface detecting the write transaction.
Claim 3
Dependent Claim
327 words
A computer system comprising: a. a main memory means including a plurality of addressable storage locations for storing data and for generating memory control signals; b. a plurality of processors for processing data, each of said processors including: i. a central processing unit for processing data in response to instructions and for initiating transactions that access addressable storage locations in said main memory means, said central processing unit including a primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for indicating memory addresses of the data stored in said primary cache memory; and ii. a cache controller including a secondary cache memory for storing a subset of the data stored in said main memory, a secondary cache tag store for indicating memory addresses of the data stored in said second cache memory and a primary cache tag store copy means for storing a copy of said primary cache tag store; d. a system bus for intercoupling said main memory and said processors and for intercoupling each of said processors to any other processor; e. each of said processors further including a memory interface providing means for receiving write transactions detected on the system bus, said memory interface including i. coupling means coupling said memory interface to said system bus for monitoring write transactions on said system bus; ii. invalidate bus means for transmitting memory addresses associated with detected write transactions to said cache controller; and iii. processor bus means for coupling said memory interface with said cache controller and with said central processing unit wherein, if a memory address transmitted by said memory interface to said cache controller is resident in either the copy of the primary cache tag store or said secondary cache tag store, the memory address is transmitted on said processor bus by the memory interface to the cache controller as an invalidate, otherwise, said write transaction is ignored by said processor.
Claim 4
Dependent Claim
327 words
A computer system comprising: a. a main memory means including a plurality of addressable storage locations for storing data and for generating memory control signals; b. a plurality of processors for processing data, each of said processors including: i. a central processing unit for processing data in response to instructions and for initiating transactions that access addressable storage locations in said main memory means, said central processing unit including a primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for indicating memory addresses of the data stored in said primary cache memory; and ii. a cache controller including a secondary cache memory for storing a subset of the data stored in said main memory, a secondary cache tag store for indicating memory addresses of the data stored in said second cache memory and a primary cache tag store copy means for storing a copy of said primary cache tag store; d. a system bus for intercoupling said main memory and said processors and for intercoupling each of said processors to any other processor; e. each of said processors further including a memory interface providing means for receiving write transactions detected on the system bus, said memory interface including i. coupling means coupling said memory interface to said system bus for monitoring write transactions on said system bus; ii. invalidate bus means for transmitting memory addresses associated with detected write transactions to said cache controller; and iii. processor bus means for coupling said memory interface with said cache controller and with said central processing unit wherein, if a memory address transmitted by said memory interface to said cache controller is resident in either the copy of the primary cache tag store or said secondary cache tag store, the memory address is transmitted on said processor bus by the memory interface to the cache controller as an invalidate, otherwise, said write transaction is ignored by said processor.
Claim 5
Independent Claim
240 words
A method of operating a computer system, the computer system having a main memory for storing blocks of data, said computer system further having a plurality of processors each of said processors capable of issuing write transactions defining invalidate requests, said computer system further having a system bus for intercoupling said main memory and said processors, each of said processors having an associated primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for identifying blocks of memory addresses resident in said primary cache memory, each of said processors further having a memory interface for detecting write transactions on said system bus, each of said processors further having a cache controller coupled to said memory interface by an invalidate bus, said cache controller including a copy of the primary cache tag store, said method of operating including filtering invalidate requests by the steps of: a. detecting a write transaction on the system bus, said write transaction defining a memory location in said main memory; b. forwarding the memory address so defined to the cache controller by way of said invalidate bus; c. comparing said memory address to memory addresses identified in said copy of the primary cache tag store; and d. if said memory address is indicated in said copy of the primary cache tag store, issuing an invalidate request on the processor bus, otherwise ignoring said write transaction.
Claim 6
Independent Claim
240 words
A method of operating a computer system, the computer system having a main memory for storing blocks of data, said computer system further having a plurality of processors each of said processors capable of issuing write transactions defining invalidate requests, said computer system further having a system bus for intercoupling said main memory and said processors, each of said processors having an associated primary cache memory for storing a subset of the data stored in said main memory and a primary cache tag store for identifying blocks of memory addresses resident in said primary cache memory, each of said processors further having a memory interface for detecting write transactions on said system bus, each of said processors further having a cache controller coupled to said memory interface by an invalidate bus, said cache controller including a copy of the primary cache tag store, said method of operating including filtering invalidate requests by the steps of: a. detecting a write transaction on the system bus, said write transaction defining a memory location in said main memory; b. forwarding the memory address so defined to the cache controller by way of said invalidate bus; c. comparing said memory address to memory addresses identified in said copy of the primary cache tag store; and d. if said memory address is indicated in said copy of the primary cache tag store, issuing an invalidate request on the processor bus, otherwise ignoring said write transaction.
Claim 7
Dependent Claim
45 words
A method according to claim 3 wherein said cache controller includes a secondary cache memory for storing a subset of the data stored in said main memory and a secondary cache tag store for identifying blocks of memory addresses resident in said secondary cache memory.
Claim 8
Dependent Claim
41 words
A method according to claim 4 including the steps of comparing said memory address to memory addresses identified in said secondary cache tag store, and if said memory address is indicated in said secondary cache tag store issuing said invalidate request.
Claim 9
Dependent Claim
299 words
A computer system comprising: a. a main memory means including a plurality of addressable storage locations for storing data and for generating memory control signals; b. a plurality of processors for processing data, each of said processors including: i. a central processing unit for processing data in response to instructions and for initiating transactions that access addressable storage locations in said main memory means, said central processing unit including a cache memory for storing a subset of the data stored in said main memory and a cache tag store for indicating memory addresses of the data stored in said primary cache memory; and ii. a cache controller including a cache tag store copy means for storing a copy of said cache tag store and a secondary cache memory for storing a subset of the data stored in said main memory and a secondary cache tag store for identifying blocks of memory addresses resident in said secondary cache memory; c. a system bus for intercoupling said main memory and said processors and for intercoupling each of said processors to any other processor; d. each of said processors further including a memory interface coupled to said system bus, said memory interface providing means for receiving write transactions detected on said system bus, the memory interface including i. invalidate bus means for transmitting memory addresses associated with detected write transactions to said cache controller; and ii. processor bus means for coupling said memory interface with said central processing unit; wherein, if a memory address transmitted by said memory interface to said cache controller is resident in either said copy of said cache tag store or in said secondary cache tag store, the memory address is transmitted on said processor bus as an invalidate, otherwise, said write transaction is ignored by said processor.
Claim 10
Dependent Claim
299 words
A computer system comprising: a. a main memory means including a plurality of addressable storage locations for storing data and for generating memory control signals; b. a plurality of processors for processing data, each of said processors including: i. a central processing unit for processing data in response to instructions and for initiating transactions that access addressable storage locations in said main memory means, said central processing unit including a cache memory for storing a subset of the data stored in said main memory and a cache tag store for indicating memory addresses of the data stored in said primary cache memory; and ii. a cache controller including a cache tag store copy means for storing a copy of said cache tag store and a secondary cache memory for storing a subset of the data stored in said main memory and a secondary cache tag store for identifying blocks of memory addresses resident in said secondary cache memory; c. a system bus for intercoupling said main memory and said processors and for intercoupling each of said processors to any other processor; d. each of said processors further including a memory interface coupled to said system bus, said memory interface providing means for receiving write transactions detected on said system bus, the memory interface including i. invalidate bus means for transmitting memory addresses associated with detected write transactions to said cache controller; and ii. processor bus means for coupling said memory interface with said central processing unit; wherein, if a memory address transmitted by said memory interface to said cache controller is resident in either said copy of said cache tag store or in said secondary cache tag store, the memory address is transmitted on said processor bus as an invalidate, otherwise, said write transaction is ignored by said processor.
Claim 11
Dependent Claim
34 words
plurality of a. a main memory means including a addressable storage locations for storing data and for generating memory control signals; b. a plurality of processors for processing data, each of said processors including:
Claim 12
Dependent Claim
34 words
plurality of a. a main memory means including a addressable storage locations for storing data and for generating memory control signals; b. a plurality of processors for processing data, each of said processors including:
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |