US5307477A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-level cache memory system
Assignee: MIPS Tech LLC
•
Filing: 1993-05-10
•
Granted: 1994-04-26
•
Expires: 2013-05-10
Abstract
Abstract A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.
Inventors
- 👤 George S. Taylor
- 👤 P. Michael Farmwald
- 👤 Timothy P. Layman
- 👤 Huy X. Ngo
- 👤 Allen W. Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:12
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0891; G06F12/0888; G06F12/0893; G06F12/0897; G06F12/10; G06F12/1027; G06F12/1045
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
328 words
A cache memory system comprising: processing means for generating a virtual address; a primary cache memory, comprising: primary cache tag means containing a plurality of primary virtual tags, the primary cache tag means connected to receive at least a portion of the virtual address from the processing means and supply in response a corresponding primary cache virtual tag to the processing means; primary instruction cache means containing a plurality of instructions and a first plurality of virtual tags, the primary instructions and a first plurality of virtual tags, the primary instruction cache means connected to receive at least a portion of the virtual address from the processing means and supply in response a corresponding instruction from the plurality of instructions to the processing means; and primary data cache means containing a second plurality of primary virtual tags and a plurality of data units, the primary data cache means also connected to receive at least a portion of the virtual address from the processing means and in response to supply a corresponding data unit from the plurality of data units to the processing means; translation means connected to receive the virtual address form the processing and translate the virtual address into a physical address; and a secondary cache memory, comprising: secondary cache tag means containing a plurality of secondary virtual tags, the secondary cache tag means connected to receive at least a portion of the physical address from the translation means and supply in response a corresponding secondary virtual tag to the processing means; and secondary cache means containing a plurality of instructions and data units, the secondary cache means connected to receive at least a portion of the physical address from the translation means and supply in response a corresponding instruction or data unit from the plurality of instructions and data to the processing means; wherein the primary cache memory employs a virtual addressing scheme, thereby eliminating the need for address translation to access the primary cache memory.
Claim 2
Dependent Claim
328 words
A cache memory system comprising: processing means for generating a virtual address; a primary cache memory, comprising: primary cache tag means containing a plurality of primary virtual tags, the primary cache tag means connected to receive at least a portion of the virtual address from the processing means and supply in response a corresponding primary cache virtual tag to the processing means; primary instruction cache means containing a plurality of instructions and a first plurality of virtual tags, the primary instructions and a first plurality of virtual tags, the primary instruction cache means connected to receive at least a portion of the virtual address from the processing means and supply in response a corresponding instruction from the plurality of instructions to the processing means; and primary data cache means containing a second plurality of primary virtual tags and a plurality of data units, the primary data cache means also connected to receive at least a portion of the virtual address from the processing means and in response to supply a corresponding data unit from the plurality of data units to the processing means; translation means connected to receive the virtual address form the processing and translate the virtual address into a physical address; and a secondary cache memory, comprising: secondary cache tag means containing a plurality of secondary virtual tags, the secondary cache tag means connected to receive at least a portion of the physical address from the translation means and supply in response a corresponding secondary virtual tag to the processing means; and secondary cache means containing a plurality of instructions and data units, the secondary cache means connected to receive at least a portion of the physical address from the translation means and supply in response a corresponding instruction or data unit from the plurality of instructions and data to the processing means; wherein the primary cache memory employs a virtual addressing scheme, thereby eliminating the need for address translation to access the primary cache memory.
Claim 3
Dependent Claim
23 words
A cache memory system as in claim 1 wherein the secondary cache means further includes a reserved section for storing secondary physical tags.
Claim 4
Dependent Claim
23 words
A cache memory system as in claim 1 wherein the secondary cache memory includes a reserved portion for storing translation lookaside buffer information.
Claim 5
Dependent Claim
214 words
A computing system comprising: a processing unit for processing data under control of instructions; translation means coupled to the processing unit for translating a virtual address into a physical address; primary cache tag means coupled to receive at least a portion of the virtual address from the processing unit for supplying primary cache virtual tags to the processing unit; secondary cache tag means coupled to receive at least a portion of the physical address from the translation means for supplying secondary cache virtual tags to the processing unit; primary instruction cache means coupled to receive at least a portion of the virtual address from the processing unit for supplying instructions to the processing unit; primary data cache means coupled to receive at least a portion of the virtual address from the processing unit for supplying data to the processing unit; and secondary cache means coupled to receive at least a portion of the physical address from the translation means for supplying instructions and data to the processing unit; wherein the primary cache tag means, the primary instruction cache means, and the primary data cache means are part of a primary cache memory, the primary cache memory employing a virtual addressing scheme, thereby eliminating the need for address translation to access the primary cache memory.
Claim 6
Dependent Claim
214 words
A computing system comprising: a processing unit for processing data under control of instructions; translation means coupled to the processing unit for translating a virtual address into a physical address; primary cache tag means coupled to receive at least a portion of the virtual address from the processing unit for supplying primary cache virtual tags to the processing unit; secondary cache tag means coupled to receive at least a portion of the physical address from the translation means for supplying secondary cache virtual tags to the processing unit; primary instruction cache means coupled to receive at least a portion of the virtual address from the processing unit for supplying instructions to the processing unit; primary data cache means coupled to receive at least a portion of the virtual address from the processing unit for supplying data to the processing unit; and secondary cache means coupled to receive at least a portion of the physical address from the translation means for supplying instructions and data to the processing unit; wherein the primary cache tag means, the primary instruction cache means, and the primary data cache means are part of a primary cache memory, the primary cache memory employing a virtual addressing scheme, thereby eliminating the need for address translation to access the primary cache memory.
Claim 7
Dependent Claim
17 words
A computing system as in claim 4 wherein the secondary cache tag means also includes physical tags.
References Cited (Backward Citations)
US4464712A
Cited
US4442487A
Cited
US4707784A
Cited
US4612612A
Cited
US4701844A
Cited
US4807110A
Cited
US4736293A
Cited
US4823259A
Cited
US4985829A
Cited
US4991081A
Cited
US4774654A
Cited
US4755930A
Cited
US4713755A
Cited
US4797814A
Cited
US4785395A
Cited
US5095424A
Cited
US4980823A
Cited
US4926317A
Cited
US5018061A
Cited
US4831622A
Cited
US5023776A
Cited
US5058006A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-25 | 1997-10-25 | 1998-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-25 | 2001-10-25 | 2002-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-25 | 2005-10-25 | 2006-04-26 | $7700.00 | Window Closed / Lapsed |