System and method for achieving buffer memory coincidence in a multiprocessor system

Claim 1

A method for achieving buffer memory coincidence in a multiprocessor system comprising the steps of: providing a plurality of central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, a main memory commonly utilized by said central processing units, and an intermediate buffer memory operatively connected between said main memory and said buffer memories, said intermediate buffer memory having a plurality of data block memory areas for storing respective corresponding data blocks, and a plurality of supervising information memory areas, one for each data block memory area, each supervising information memory area being coupled to a respective corresponding one of said data block memory areas, each supervising information memory area storing supervising information indicating whether or not a copy of one of said respective corresponding data blocks stored in said respective corresponding one of said data block memory areas is stored in each of said buffer memories; detecting when one of said central processing units provides a request for accessing a data block in said intermediate buffer memory; detecting whether or not said request is a request sent to said intermediate buffer memory for writing a data block; if said request is a request for writing a data block, detecting whether or not the accessed data block is found in said intermediate buffer memory; if said accessed data block is not found in said intermediate buffer memory, sending buffer invalidation address information to all of said buffer memories other than the buffer memory contained in the accessing central processing unit, said buffer invalidation address information having an address identical to the address of said accessed data block; if said accessed data block is found in said intermediate buffer memory, sending said buffer invalidation address information only to selected ones of said buffer memories, said selected ones of said buffer memories being determined by said intermediate buffer memory in accordance with said supervising information.

Claim 2

A method for achieving buffer memory coincidence in a multiprocessor system comprising the steps of: providing a plurality of central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, a main memory commonly utilized by said central processing units, and an intermediate buffer memory operatively connected between said main memory and said buffer memories, said intermediate buffer memory having a plurality of data block memory areas for storing respective corresponding data blocks, and a plurality of supervising information memory areas, one for each data block memory area, each supervising information memory area being coupled to a respective corresponding one of said data block memory areas, each supervising information memory area storing supervising information indicating whether or not a copy of one of said respective corresponding data blocks stored in said respective corresponding one of said data block memory areas is stored in each of said buffer memories; detecting when one of said central processing units provides a request for accessing a data block in said intermediate buffer memory; detecting whether or not said request is a request sent to said intermediate buffer memory for writing a data block; if said request is a request for writing a data block, detecting whether or not the accessed data block is found in said intermediate buffer memory; if said accessed data block is not found in said intermediate buffer memory, sending buffer invalidation address information to all of said buffer memories other than the buffer memory contained in the accessing central processing unit, said buffer invalidation address information having an address identical to the address of said accessed data block; if said accessed data block is found in said intermediate buffer memory, sending said buffer invalidation address information only to selected ones of said buffer memories, said selected ones of said buffer memories being determined by said intermediate buffer memory in accordance with said supervising information.

Claim 11

A method for achieving buffer memory coincidence in a multiprocessor system, comprising the steps of: providing a plurality of central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, a main memory commonly utilized by said central processing units, and an intermediate buffer memory; checking in accordance with the contents of said intermediate buffer memory, the following six kinds of information: REQ.CPU, W, F, F, copy #1 and VIF; and producing information of BIA GO #i indicating that buffer invalidation address information must be sent to the i-th (i=1,2,3 . . . ) central processing unit, in accordance with the logical expression: BIA GO #1=REQ.CPU×W×{FvF×(COPY #1v VIF} where the term "REQ.CPU" indicates that the i-th central processing unit does not provide a request for accessing said intermediate buffer memory, the term "W" indicates that the above request is a request for writing a data block, the terms "F" and "F" indicate that the accessed data block is found or is not found, respectively, in said intermediate buffer memory, the term "COPY #1" indicates a copy of a corresponding data block is stored in said buffer memory of said i-th central processing unit, the term VIF indicates the possibility that the copy flags may be invalid, and the symbols "x" and "v" represent a logical product and a logical sum, respectively.

Claim 12

A method for achieving buffer memory coincidence in a multiprocessor system, comprising the steps of: providing a plurality of central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, a main memory commonly utilized by said central processing units, and an intermediate buffer memory; checking in accordance with the contents of said intermediate buffer memory, the following six kinds of information: REQ.CPU, W, F, F, copy #1 and VIF; and producing information of BIA GO #i indicating that buffer invalidation address information must be sent to the i-th (i=1,2,3 . . . ) central processing unit, in accordance with the logical expression: BIA GO #1=REQ.CPU×W×{FvF×(COPY #1v VIF} where the term "REQ.CPU" indicates that the i-th central processing unit does not provide a request for accessing said intermediate buffer memory, the term "W" indicates that the above request is a request for writing a data block, the terms "F" and "F" indicate that the accessed data block is found or is not found, respectively, in said intermediate buffer memory, the term "COPY #1" indicates a copy of a corresponding data block is stored in said buffer memory of said i-th central processing unit, the term VIF indicates the possibility that the copy flags may be invalid, and the symbols "x" and "v" represent a logical product and a logical sum, respectively.

Claim 13

A method for achieving buffer memory coincidence in a multiprocessor system, comprising the steps of: (a) providing a plurality of central processing units, a main memory commonly utilized by said central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, and an intermediate buffer memory operatively connected between said main memory and said buffer memories, said intermediate buffer memory having a plurality of data block memory areas for storing respective corresponding data blocks and a plurality of copy flags storage areas for holding copy flags, one for each buffer memory; (b) detecting when one of said central processing units provides a request for accessing a data block in said intermediate buffer memory; (c) detecting whether or not the accessed data block is found in said intermediate buffer memory; (d) if said accessed data block is not found in said intermediate buffer memory, sending buffer invalidation address information to all buffer memories other than the buffer memory of the accessing central processing unit; (e) if said accessed data block is found in said intermediate buffer memory, selectively setting or resetting said copy flag corresponding to said buffer memory of said accessing central processing unit in accordance with whether said accessed data block has been found or has not been found, respectively, in the buffer memory of said accessing central processing unit.

Claim 14

A method for achieving buffer memory coincidence in a multiprocessor system, comprising the steps of: (a) providing a plurality of central processing units, a main memory commonly utilized by said central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, and an intermediate buffer memory operatively connected between said main memory and said buffer memories, said intermediate buffer memory having a plurality of data block memory areas for storing respective corresponding data blocks and a plurality of copy flags storage areas for holding copy flags, one for each buffer memory; (b) detecting when one of said central processing units provides a request for accessing a data block in said intermediate buffer memory; (c) detecting whether or not the accessed data block is found in said intermediate buffer memory; (d) if said accessed data block is not found in said intermediate buffer memory, sending buffer invalidation address information to all buffer memories other than the buffer memory of the accessing central processing unit; (e) if said accessed data block is found in said intermediate buffer memory, selectively setting or resetting said copy flag corresponding to said buffer memory of said accessing central processing unit in accordance with whether said accessed data block has been found or has not been found, respectively, in the buffer memory of said accessing central processing unit.

Claim 17

A method for achieving buffer memory coincidence in a multiprocessor system, comprising the steps of: (a) providing a plurality of central processing units, a main memory commonly utilized by said central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, and an intermediate buffer memory operatively connected between said main memory and said buffer memories, said intermediate buffer memory having a plurality of data block memory areas for storing respective corresponding data blocks and a plurality of copy flags storage areas for holding copy flags, one for each buffer memory; (b) detecting when one of said central processing units provides a request for accessing a data block in said intermediate buffer memory; (c) detecting whether or not the accessed data block is found in said intermediate buffer memory; (d) if said accessed data block is not found in said intermediate buffer memory, transferring said accessed data block into said intermediate buffer memory; (e) determining whether or not said request for access is a writing or reading operation; (f) if said request for access is a writing operation, selectively setting or resetting said copy flag of said buffer memory of said accessing central processing unit in accordance with whether said accessed data block has been found or has not been found, respectively, in said buffer memory of said accessing central processing unit; (g) if said request for access is a reading operation, setting said copy flag of said buffer memory of said accessing central processing unit.

Claim 18

A method for achieving buffer memory coincidence in a multiprocessor system, comprising the steps of: (a) providing a plurality of central processing units, a main memory commonly utilized by said central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, and an intermediate buffer memory operatively connected between said main memory and said buffer memories, said intermediate buffer memory having a plurality of data block memory areas for storing respective corresponding data blocks and a plurality of copy flags storage areas for holding copy flags, one for each buffer memory; (b) detecting when one of said central processing units provides a request for accessing a data block in said intermediate buffer memory; (c) detecting whether or not the accessed data block is found in said intermediate buffer memory; (d) if said accessed data block is not found in said intermediate buffer memory, transferring said accessed data block into said intermediate buffer memory; (e) determining whether or not said request for access is a writing or reading operation; (f) if said request for access is a writing operation, selectively setting or resetting said copy flag of said buffer memory of said accessing central processing unit in accordance with whether said accessed data block has been found or has not been found, respectively, in said buffer memory of said accessing central processing unit; (g) if said request for access is a reading operation, setting said copy flag of said buffer memory of said accessing central processing unit.

Claim 21

A system for achieving buffer memory coincidence in a multiprocessor system, said multiprocessor system comprising a plurality of central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, a main memory commonly utilized by said central processing units, and an intermediate buffer memory operatively connected between said main memory and said buffer memories, said intermediate buffer memory having a plurality of data block memory areas for storing respective corresponding data blocks, and a plurality of supervising information memory areas, one for each data block memory area, each supervising information memory area being coupled to a respective corresponding one of said data block memory areas, each supervising information memory area storing supervising information indicating whether or not a copy of said respective corresponding data block stored in said respective corresponding one of said data block memory areas is stored in each of said buffer memories; said system for achieving buffer memory coincidence comprising: means for detecting when one of said central processing units provides a request for accessing a data block in said intermediate buffer memory; means for detecting whether or not said request is a request sent to said intermediate buffer memory for writing a data block; means for detecting, when said request is a request for writing a data block, whether or not said accessed data block is found in said intermediate buffer memory; means for sending, when said accessed data block is not found in said intermediate buffer memory, buffer invalidation address information to all of said buffer memories other than the buffer memory contained in said accessing central processing unit, said buffer invalidation address information having an address identical to the address of said accessed data block; means for sending, if said accessed data block is found in said intermediate buffer memory, said buffer invalidation address information only to selected ones of said buffer memories, said selected ones of said buffer memories being determined by said intermediate buffer memory in accordance with said supervising information.

Claim 22

A system for achieving buffer memory coincidence in a multiprocessor system, said multiprocessor system comprising a plurality of central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, a main memory commonly utilized by said central processing units, and an intermediate buffer memory operatively connected between said main memory and said buffer memories, said intermediate buffer memory having a plurality of data block memory areas for storing respective corresponding data blocks, and a plurality of supervising information memory areas, one for each data block memory area, each supervising information memory area being coupled to a respective corresponding one of said data block memory areas, each supervising information memory area storing supervising information indicating whether or not a copy of said respective corresponding data block stored in said respective corresponding one of said data block memory areas is stored in each of said buffer memories; said system for achieving buffer memory coincidence comprising: means for detecting when one of said central processing units provides a request for accessing a data block in said intermediate buffer memory; means for detecting whether or not said request is a request sent to said intermediate buffer memory for writing a data block; means for detecting, when said request is a request for writing a data block, whether or not said accessed data block is found in said intermediate buffer memory; means for sending, when said accessed data block is not found in said intermediate buffer memory, buffer invalidation address information to all of said buffer memories other than the buffer memory contained in said accessing central processing unit, said buffer invalidation address information having an address identical to the address of said accessed data block; means for sending, if said accessed data block is found in said intermediate buffer memory, said buffer invalidation address information only to selected ones of said buffer memories, said selected ones of said buffer memories being determined by said intermediate buffer memory in accordance with said supervising information.

Claim 31

A system for achieving buffer memory coincidence in a multiprocessing system, comprising a plurality of central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, a main memory commonly utilized by said central processing units, and an intermediate buffer memory; said system further comprising: means for checking, in accordance with said intermediate buffer memory, for the following logical conditions: REQ.CPU, W, F, F, copy #i and VIF; and means for producing information BIA GO #i, indicating that a buffer invalidation address information must be sent to the i-th (i=1, 2, 3 . . . ) central processing unit, in accordance with conditions corresponding to the following logical expression: BIA GO #i=REQ.CPU×W×{FvF×(COPY#i v/VIF} where the term "REQ.CPU" indicates that the i=th central processing unit does not provide a request for accessing said intermediate buffer memory, the term "W" indicates that the above request is a request for writing a data block, the terms "F" and "F" indicate that the accessed data block is found or is not found, respectively, in said intermediate buffer memory, the term "COPY #i" indicates that a copy of a corresponding data block is stored in said buffer memory of said i-th central processing unit, the term VIF indicates the possibility that at least one of the copy flags is invalid, and the symbols "X" and "v" represent a logical product and a logical sum, respectively.

Claim 32

A system for achieving buffer memory coincidence in a multiprocessing system, comprising a plurality of central processing units, a plurality of buffer memories, one for each central processing unit, each buffer memory being contained in a respective one of said central processing units, a main memory commonly utilized by said central processing units, and an intermediate buffer memory; said system further comprising: means for checking, in accordance with said intermediate buffer memory, for the following logical conditions: REQ.CPU, W, F, F, copy #i and VIF; and means for producing information BIA GO #i, indicating that a buffer invalidation address information must be sent to the i-th (i=1, 2, 3 . . . ) central processing unit, in accordance with conditions corresponding to the following logical expression: BIA GO #i=REQ.CPU×W×{FvF×(COPY#i v/VIF} where the term "REQ.CPU" indicates that the i=th central processing unit does not provide a request for accessing said intermediate buffer memory, the term "W" indicates that the above request is a request for writing a data block, the terms "F" and "F" indicate that the accessed data block is found or is not found, respectively, in said intermediate buffer memory, the term "COPY #i" indicates that a copy of a corresponding data block is stored in said buffer memory of said i-th central processing unit, the term VIF indicates the possibility that at least one of the copy flags is invalid, and the symbols "X" and "v" represent a logical product and a logical sum, respectively.