Method of manufacturing semiconductor device having unit circuit-blocks

Claim 1

A method of manufacturing an application specific integrated circuit (ASIC) device on a semiconductor substrate having a resist film coated thereon, comprising: (a) forming a set of plural unit circuit blocks in mutually spaced relationship on corresponding, mutually spaced block sections of a chip area of the semiconductor substrate having the resist film thereon, each unit circuit-block having a separate, respective function and being physically separated from, and not electrically connected to, each other unit circuit-block of the set, by: a fabrication process comprising: (i) individually and in sequence for the plural unit circuit blocks of the set, selectively exposing each block section within the chip area using a respective, individual mask for each block section, to form plural, respective latent images of the plural unit circuit block patterns in said corresponding block sections of the chip area, (ii) simultaneously developing all of the latent images formed on the substrate to form a resist pattern, and (iii) using the resist pattern, further processing the substrate and completing formation of the set of plural unit circuit blocks; and (b) forming external interconnections selectively, externally interconnecting the plural unit circuit-blocks of the set formed on the chip area, by: (i) forming an interconnection layer on the plural unit circuit-blocks, (ii) coating a resist film over the interconnection layer and exposing the interconnection layer, using an interconnection mask, for making a corresponding resist pattern, and (iii) developing the corresponding resist pattern to form the external interconnections from the interconnection layer.

Claim 2

A method of manufacturing an application specific integrated circuit (ASIC) device on a semiconductor substrate having a resist film coated thereon, comprising: (a) forming a set of plural unit circuit blocks in mutually spaced relationship on corresponding, mutually spaced block sections of a chip area of the semiconductor substrate having the resist film thereon, each unit circuit-block having a separate, respective function and being physically separated from, and not electrically connected to, each other unit circuit-block of the set, by: a fabrication process comprising: (i) individually and in sequence for the plural unit circuit blocks of the set, selectively exposing each block section within the chip area using a respective, individual mask for each block section, to form plural, respective latent images of the plural unit circuit block patterns in said corresponding block sections of the chip area, (ii) simultaneously developing all of the latent images formed on the substrate to form a resist pattern, and (iii) using the resist pattern, further processing the substrate and completing formation of the set of plural unit circuit blocks; and (b) forming external interconnections selectively, externally interconnecting the plural unit circuit-blocks of the set formed on the chip area, by: (i) forming an interconnection layer on the plural unit circuit-blocks, (ii) coating a resist film over the interconnection layer and exposing the interconnection layer, using an interconnection mask, for making a corresponding resist pattern, and (iii) developing the corresponding resist pattern to form the external interconnections from the interconnection layer.

Claim 12

A method of manufacturing an intermediate production product, used for producing a corresponding customized semiconductor device, the intermediate production product comprising a set of unit circuit-blocks selected from a plurality of unit circuit-blocks having respective, individual functions, each unit circuit-block comprising plural elements internally interconnected therewithin and the corresponding customized semiconductor device further requiring external interconnections between, and selectively interconnecting, the unit circuit blocks of the corresponding intermediate production product, the method comprising the steps of: (a) providing previously designed, plural masks respectively for forming the plurality of unit circuit blocks; (b) defining, for the associated set of selected unit circuit blocks, corresponding block sections of a chip in which the selected unit circuit blocks are to be formed; (c) selecting the respective masks previously designed for forming the selected unit circuit blocks of the set; (d) individually and in sequence for the plural unit circuit blocks of the set, selectively exposing each block section within the chip area using a respective, individual mask for each block section, thereby to form, individually and in sequence, respective, plural latent images of the unit circuit block patterns in said corresponding block sections of the chip area,; and (e) simultaneously developing the plural latent images to form a resist pattern in a resist layer on the chip and, using the resist pattern, further processing the chip to produce the intermediate production product comprising the selected unit circuit blocks, including the respective, individual elements and the internal interconnections of each thereof, and wherein the selected unit circuit blocks of the associated set have no external interconnections therebetween.

Claim 13

A method of manufacturing an intermediate production product, used for producing a corresponding customized semiconductor device, the intermediate production product comprising a set of unit circuit-blocks selected from a plurality of unit circuit-blocks having respective, individual functions, each unit circuit-block comprising plural elements internally interconnected therewithin and the corresponding customized semiconductor device further requiring external interconnections between, and selectively interconnecting, the unit circuit blocks of the corresponding intermediate production product, the method comprising the steps of: (a) providing previously designed, plural masks respectively for forming the plurality of unit circuit blocks; (b) defining, for the associated set of selected unit circuit blocks, corresponding block sections of a chip in which the selected unit circuit blocks are to be formed; (c) selecting the respective masks previously designed for forming the selected unit circuit blocks of the set; (d) individually and in sequence for the plural unit circuit blocks of the set, selectively exposing each block section within the chip area using a respective, individual mask for each block section, thereby to form, individually and in sequence, respective, plural latent images of the unit circuit block patterns in said corresponding block sections of the chip area,; and (e) simultaneously developing the plural latent images to form a resist pattern in a resist layer on the chip and, using the resist pattern, further processing the chip to produce the intermediate production product comprising the selected unit circuit blocks, including the respective, individual elements and the internal interconnections of each thereof, and wherein the selected unit circuit blocks of the associated set have no external interconnections therebetween.