Process for fabricating an integrated circuit by a repetition of exposure of a semiconductor pattern

Claim 1

A method for fabricating a semiconductor device on a substrate, comprising the steps of: defining a plurality of regions on the substrate; exposing a first pattern that extends over a plurality of said regions such that said first pattern is exposed on said plurality of regions simultaneously; and exposing a plurality of second patterns that are identical in size and shape and isolated from each other, consecutively for each of said plurality of regions.

Claim 2

A method for fabricating a semiconductor device on a substrate, comprising the steps of: defining a plurality of regions on the substrate; exposing a first pattern that extends over a plurality of said regions such that said first pattern is exposed on said plurality of regions simultaneously; and exposing a plurality of second patterns that are identical in size and shape and isolated from each other, consecutively for each of said plurality of regions.

Claim 7

A method for fabricating a semiconductor device, comprising the steps of: providing an insulation layer on a device region defined on a surface of a substrate; providing a resist layer on said insulation layer; defining a plurality of sub-regions on said device region; exposing a pattern of a contact hole on said resist layer repeatedly for each of said plurality of sub-regions; forming a plurality of windows in said resist layer in correspondence to the exposed pattern of the contact holes by developing said resist layer; forming a plurality of contact holes in correspondence to said plurality of windows while using the resist layer as a mask; and providing a device pattern that extends over a plurality of said sub-regions such that the device pattern is exposed simultaneously for the entire subregions.

Claim 8

A method for fabricating a semiconductor device, comprising the steps of: providing an insulation layer on a device region defined on a surface of a substrate; providing a resist layer on said insulation layer; defining a plurality of sub-regions on said device region; exposing a pattern of a contact hole on said resist layer repeatedly for each of said plurality of sub-regions; forming a plurality of windows in said resist layer in correspondence to the exposed pattern of the contact holes by developing said resist layer; forming a plurality of contact holes in correspondence to said plurality of windows while using the resist layer as a mask; and providing a device pattern that extends over a plurality of said sub-regions such that the device pattern is exposed simultaneously for the entire subregions.

Claim 10

A method for fabricating a semiconductor memory device comprising a plurality of memory cells formed in a device region that is defined on a surface of a substrate, comprising the steps of: forming a plurality of memory cell regions on said device region such that each memory cell region is surrounded laterally by a first insulation layer that covers the surface of the substrate; depositing a first conductor layer on said substrate in correspondence to said device region such that the first conductor layer covers the memory cell regions and said first insulation layer; patterning the first conductor layer to form a word line extending over said device region; depositing a second insulation layer on the substrate to cover the device region and the first insulation layer, said second insulation layer being deposited to bury said word line underneath; applying a first photoresist layer on said second insulation layer, exposing the first photoresist layer by a pattern of a first contact hole that is used to connect a bit line to a first diffusion region formed in the substrate, said step of exposing the first photoresist layer being achieved by defining a plurality of sub-regions on said device region and conducting an exposure of the first contact hole consecutively sub-region by sub-region; developing the first photoresist layer to form a mask having a window in correspondence to where the first contact hole is to be formed; forming the first contact hole by applying an etching via said window to expose the first diffusion region in the substrate while using the first photoresist as a mask; depositing a second conductor layer on said second insulation layer in contact with said first diffusion region via said first contact hole; patterning the second conductor layer to form a bit line that extends over the device region; depositing a third insulation layer on said second insulation layer to bury the bit line underneath; depositing a conductor layer and an insulation layer alternately on said third insulation layer to form a layered structure that comprises an alternate repetition of the conductor layer and the insulation layer; applying a second photoresist layer on said layered structure; exposing the second photoresist layer by a pattern of a second contact hole that is used to connect a memory cell capacitor to a second diffusion region formed in the substrate, said step of exposing the second photoresist layer being achieved by conducting an exposure of said second contact hole consecutively sub-region by sub-region; developing the second photoresist layer to form a second window in correspondence to where the second contact hole is to be formed; forming the second contact hole by applying an etching via said second contact hole to expose the second diffusion region in the substrate while using the second photoresist layer as a mask; patterning the layered structure to form an isolated capacitor body in correspondence to each memory cell region.

Claim 11

A method for fabricating a semiconductor memory device comprising a plurality of memory cells formed in a device region that is defined on a surface of a substrate, comprising the steps of: forming a plurality of memory cell regions on said device region such that each memory cell region is surrounded laterally by a first insulation layer that covers the surface of the substrate; depositing a first conductor layer on said substrate in correspondence to said device region such that the first conductor layer covers the memory cell regions and said first insulation layer; patterning the first conductor layer to form a word line extending over said device region; depositing a second insulation layer on the substrate to cover the device region and the first insulation layer, said second insulation layer being deposited to bury said word line underneath; applying a first photoresist layer on said second insulation layer, exposing the first photoresist layer by a pattern of a first contact hole that is used to connect a bit line to a first diffusion region formed in the substrate, said step of exposing the first photoresist layer being achieved by defining a plurality of sub-regions on said device region and conducting an exposure of the first contact hole consecutively sub-region by sub-region; developing the first photoresist layer to form a mask having a window in correspondence to where the first contact hole is to be formed; forming the first contact hole by applying an etching via said window to expose the first diffusion region in the substrate while using the first photoresist as a mask; depositing a second conductor layer on said second insulation layer in contact with said first diffusion region via said first contact hole; patterning the second conductor layer to form a bit line that extends over the device region; depositing a third insulation layer on said second insulation layer to bury the bit line underneath; depositing a conductor layer and an insulation layer alternately on said third insulation layer to form a layered structure that comprises an alternate repetition of the conductor layer and the insulation layer; applying a second photoresist layer on said layered structure; exposing the second photoresist layer by a pattern of a second contact hole that is used to connect a memory cell capacitor to a second diffusion region formed in the substrate, said step of exposing the second photoresist layer being achieved by conducting an exposure of said second contact hole consecutively sub-region by sub-region; developing the second photoresist layer to form a second window in correspondence to where the second contact hole is to be formed; forming the second contact hole by applying an etching via said second contact hole to expose the second diffusion region in the substrate while using the second photoresist layer as a mask; patterning the layered structure to form an isolated capacitor body in correspondence to each memory cell region.