EP0283655A2 — A method of combining gate array and standard cel…

Claim 1

Independent Claim 224 words

A method of making a logic chip which includes the steps of defining a plurality n of cell locations (12), each having a boundary (18), within a semiconductor chip (10), forming a plurality n - x standard cells (22, 58) within n - x of said plurality n of cell locations (12), where x is a smaller number than n, x cell locations being unoccupied, each of said standard cells having an active circuit area (24) disposed at least a given distance from the boundary (18) of its associated cell location, and forming a plurality of gate array cells (54, 56) within said unoccupied cell locations, said plurality of gate array cells being equal to or less than x, each of said gate array cells having an active circuit area disposed at least said given distance from the boundary (18) on one side of its associated cell location and extending without the boundary (18) on the side of its associated cell location opposite to that of said one side for a distance at least equal to said given distance to contact the active circuit area of an adjacent one of said plurality of gate array cells and extending to within said opposite boundary no closer than at least said given distance when one of said standard cells is disposed adjacent to said opposite boundary.

Claim 2

Independent Claim 224 words

A method of making a logic chip which includes the steps of defining a plurality n of cell locations (12), each having a boundary (18), within a semiconductor chip (10), forming a plurality n - x standard cells (22, 58) within n - x of said plurality n of cell locations (12), where x is a smaller number than n, x cell locations being unoccupied, each of said standard cells having an active circuit area (24) disposed at least a given distance from the boundary (18) of its associated cell location, and forming a plurality of gate array cells (54, 56) within said unoccupied cell locations, said plurality of gate array cells being equal to or less than x, each of said gate array cells having an active circuit area disposed at least said given distance from the boundary (18) on one side of its associated cell location and extending without the boundary (18) on the side of its associated cell location opposite to that of said one side for a distance at least equal to said given distance to contact the active circuit area of an adjacent one of said plurality of gate array cells and extending to within said opposite boundary no closer than at least said given distance when one of said standard cells is disposed adjacent to said opposite boundary.

Claim 3

Dependent Claim 89 words

A method as set forth in Claim 1 further including the steps of forming a plurality of input/output cell locations (14) along the periphery of said chip (10), a first plurality (62, 64) of said input/output cell locations having an isolation region (16) spaced from the edge of said chip (10) by a first distance and a second plurality (66, 68) of said input/output cell locations having an isolation region (16ʹ) spaced from the edge of said chip by a second distance different from that of said first distance.

Claim 4

Dependent Claim 31 words

A method as set forth in claim 2 wherein said isolation regions (16, 16ʹ) form a guard ring dividing each of said input/output cell locations (14) into first and second regions.

Claim 5

Dependent Claim 58 words

A method as set forth in claim 3 further including the steps of forming input/output circuits having a plurality of transistors in each of said input/output cell locations (14), said first region of each of said input/output cell locations having formed therein at least one of said transistors with the remaining transistors being formed within said second regions.

Claim 6

Independent Claim 208 words

A method as set forth in claims 1 to 4 including the steps of defining a plurality of contiguous cell locations (12), each having a boundary (18), within a semiconductor chip (10), forming first and second standard cell circuits (22, 58) in spaced apart first and second cell locations, respectively, of said plurality of cell locations, each of said standard cell circuits being disposed within an active area (22) of its associated cell location spaced at least a given distance from the boundary (18) of its associated cell location, forming a first gate array cell (54) in a third cell location of said plurality of cell locations contiguous with said first cell location between said first and second cell locations, said first gate array cell having an active circuit area spaced at least a given distance from the common boundary (18) between said first and third cell locations, and forming a second gate array cell (56) in a fourth cell location of said plurality of cell locations contiguous to said second cell location between said first and second cell locations, said second gate array cell having an active circuit area spaced at least said given distance from the common boundary (18) between said second and fourth cell locations.

Claim 7

Dependent Claim 86 words

A method as set forth in claim 5 wherein said first gate array cell (54) includes a given number of source/drain diffusion regions (46A, 46B, 46C, 50A, 50B, 50C) of a first conductivity type within its cell location boundary (18) and one source/drain diffusion region (46D, 50D) without its cell location boundary (18) and said second gate array cell (56) includes only said given number of source/drain diffusion regions (46A, 46B, 46C, 50A, 50B, 50C) of said first conductivity type within its cell location boundary (18).

Claim 8

Dependent Claim 47 words

A method as set forth in claim 5 and 6 further including the step of forming insulating regions between the active circuit areas (22, 54) of said first and third cell locations and between the active circuit areas (58, 56) of said second and fourth cell locations.

Claim 9

Dependent Claim 40 words

A method as set forth in claim 1 to 7 further including the step of forming a row of gate array cells similar to said first gate array cell (54) between said first and second gate array cells (54, 56).

Claim 10

Independent Claim 41 words

A method as set forth in claims 6 - 8 wherein said one source/drain diffusion region (46D, 50D) of said first gate array cell (54) overlaps one of said source/drain diffusion regions (46A, 50A) of said second gate array cell (56).

Claim 11

Independent Claim 85 words

A method as set forth in claims 8 and 9 wherein said one source/drain diffusion region (46D, 50D) of said first gate array cell (54) overlaps a source and drain region (46A, 50A) of one of the gate array cells (54) of said row of gate array cells and the one source/drain diffusion region of another of the gate array cells (54) of said row of gate array cell overlaps one of said source/drain diffusion regions (46A, 50A) of said second gate array cell (56).

Claim 12

Independent Claim 30 words

A method as set forth in claims 2 to 10 further including the step of forming gate array cells in each input/output cell of said second plurality of input/output cells.

Claim 13

Dependent Claim 72 words

A method as set forth in claim 4 wherein said first regions are formed between said isolation regions and the edge of said chip and further including the step of forming three field effect transistors in each of the first regions of said second plurality (66, 68) of cell locations (14) and two field effect transistors in each of the first regions of said first plurality (62, 64) of cell locations (14).

Claim 14

Dependent Claim 221 words

A logic structure comprising a semiconductor substrate (10) having a plurality of contiguous inner cell locations (12) and a plurality of contiguous outer cell locations (14) defined therein, said outer cell locations (14) being disposed between said inner cell locations and the edge of said substrate (10), a guard ring (16, 16ʹ) disposed along the periphery of said substrate (10) and passing through said plurality of contiguous outer cell locations (14) dividing each of said outer cell locations into first and second regions, each of the outer cell locations (14) of a first plurality of said outer cell locations having said guard ring passing therethrough at a first distance from the edge of said substrate and each of the outer cell locations of a second plurality of said outer cell locations having said guard ring passing therethrough at a second distance from the edge of said substrate, a plurality of standard cell logic circuits (22, 58) disposed within a number of said inner cell locations, a plurality of gate array logic circuits (54, 56) disposed within the remaining inner cell locations of said plurality of inner cell locations, a plurality of standard cell input/output circuits disposed within said first plurality of outer cell locations, and a plurality of gate array input/output circuits disposed within said second plurality of outer cell locations.

Claim 15

Dependent Claim 221 words

A logic structure comprising a semiconductor substrate (10) having a plurality of contiguous inner cell locations (12) and a plurality of contiguous outer cell locations (14) defined therein, said outer cell locations (14) being disposed between said inner cell locations and the edge of said substrate (10), a guard ring (16, 16ʹ) disposed along the periphery of said substrate (10) and passing through said plurality of contiguous outer cell locations (14) dividing each of said outer cell locations into first and second regions, each of the outer cell locations (14) of a first plurality of said outer cell locations having said guard ring passing therethrough at a first distance from the edge of said substrate and each of the outer cell locations of a second plurality of said outer cell locations having said guard ring passing therethrough at a second distance from the edge of said substrate, a plurality of standard cell logic circuits (22, 58) disposed within a number of said inner cell locations, a plurality of gate array logic circuits (54, 56) disposed within the remaining inner cell locations of said plurality of inner cell locations, a plurality of standard cell input/output circuits disposed within said first plurality of outer cell locations, and a plurality of gate array input/output circuits disposed within said second plurality of outer cell locations.

Claim 16

Dependent Claim 43 words

A logic structure as set forth in claim 13 wherein adjacent gate array logic circuits are contiguous and a gate array logic circuit and a standard cell logic adjacent to each other are separated from each other by a given ground rule distance.

Claim 17

Dependent Claim 23 words

A logic structure as set forhtin claim 14 wherein an insulating medium is disposed between adjacent gate array and standard cell logic circuits.

A method of combining gate array and standard cell circuits on a common semiconductor chip

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag