Layered low dielectric constant technology

Claim 2

A process for reducing capacitance between a first layer of metal interconnects in semiconductor devices, said first layer of metal interconnects separated from each other and from a second, overlying layer of metal interconnects for making contact to said first layer of metal interconnects by a dielectric material, said process comprising: (a) forming a layer of an organic spin-on-glass material filling gaps between metal interconnects in said first layer of metal interconnects; (b) etching said organic spin-on-glass material back such that said organic spin-on-material is not formed over said metal interconnects in said first layer of metal interconnects; (c) forming a layer of a chemically vapor deposited oxide on said organic spin-on-glass layer; and (d) forming a layer of an inorganic spin-on-glass material on said chemically vapor deposited oxide to provide planarization to support said second layer of metal interconnects.

Claim 3

The process of claim 1 wherein said chemically vapor deposited oxide layers comprise silicon-rich silicon dioxide.

Claim 4

The process of claim 2 wherein said chemically vapor deposited oxide layer has a thickness in the range of about 500 to 1,000 Å.

Claim 5

The process of claim 1 wherein said organic spin-on-glass material consists essentially of a high carbon-containing siloxane.

Claim 6

The process of claim 4 wherein said organic spin-on-glass layer has a thickness that is approximately one-half that of said metal first layer metal interconneet.

Claim 7

The process of claim 1 wherein said inorganic spin-on-glass material consists essentially of silicate or hydrogen silsesquioxane.

Claim 8

The process of claim 6 wherein said inorganic spin-on-glass layer has a thickness that is less than about 6,000 Å.

Claim 9

A process for reducing capacitance between a first layer of metal interconnects in semiconductor devices, said first layer of metal interconnects separated from each other and from a second, overlying layer of metal interconnects for making contact to said first layer of metal interconnects by a dielectric material, said process comprising: (a) forming a first plasma-enhanced, chemically vapor deposited oxide layer on all exposed metal surfaces of said first metal interconnect layer and exposed semiconductor surfaces to form oxide-coated metal interconnects; (b) forming an organic spin-on-glass material partially filling spaces between said first layer of metal interconnects and leaving top portions of said oxide-coated metal interconnects exposed; (c) forming a second plasma-enhanced chemically vapor deposited layer on said top portions of said oxide-coated metal interconnects and on said organic spin-on-glass layer; (d) forming a first inorganic spin-on-glass layer on said second plasma-enhanced chemically vapor deposited oxide layer; (e) forming a third plasma-enhanced chemically vapor deposited oxide layer on said first inorganic spin-on-glass layer; (f) forming a second inorganic spin-on-glass layer on said third plasma-enhanced chemically vapor deposited layer planarization; and (g) forming said second layer of metal interconnects on top of said second inorganic spin-on-glass layer.

Claim 10

A process for reducing capacitance between a first layer of metal interconnects in semiconductor devices, said first layer of metal interconnects separated from each other and from a second, overlying layer of metal interconnects for making contact to said first layer of metal interconnects by a dielectric material, said process comprising: (a) forming a first plasma-enhanced, chemically vapor deposited oxide layer on all exposed metal surfaces of said first metal interconnect layer and exposed semiconductor surfaces to form oxide-coated metal interconnects; (b) forming an organic spin-on-glass material partially filling spaces between said first layer of metal interconnects and leaving top portions of said oxide-coated metal interconnects exposed; (c) forming a second plasma-enhanced chemically vapor deposited layer on said top portions of said oxide-coated metal interconnects and on said organic spin-on-glass layer; (d) forming a first inorganic spin-on-glass layer on said second plasma-enhanced chemically vapor deposited oxide layer; (e) forming a third plasma-enhanced chemically vapor deposited oxide layer on said first inorganic spin-on-glass layer; (f) forming a second inorganic spin-on-glass layer on said third plasma-enhanced chemically vapor deposited layer planarization; and (g) forming said second layer of metal interconnects on top of said second inorganic spin-on-glass layer.

Claim 11

The process of claim 8 wherein said plasma-enhanced chemically vapor deposited oxide layers comprise silicon-rich silicon dioxide.

Claim 12

The process of claim 8 wherein said organic spin-on-glass material consists essentially of a high carbon-containing siloxane.

Claim 13

The process of claim 8 wherein said inorganic spin-on-glass material consists essentially of silicate or hydrogen silsesquioxane.

Claim 14

The process of claim 4 wherein said high carbon-containing siloxane containing comprises silsesquioxanes having alkyl functionality.

Claim 15

The process of claim 8 wherein said organic spin-on-glass material is etched back prior to forming said second plasma-enhanced chemically vapor deposited layer such that said organic spin-on-glass material is not formed on said top portions of said oxide-coated metal interconnects.

Claim 16

The process of claim 10 wherein said high carbon-containing siloxane comprises silsesquioxanes having alkyl functionality.