Electrostatic discharge protection circuit triggered by capacitive-coupling

Claim 1

An electrostatic discharge protection circuit for protecting an internal circuit, comprising: an N-type semiconductor substrate; a P-well region in the substrate; a contact region in the P-well region; an isolating structure on the substrate; a conducting layer on the isolating structure, coupled to the contact region; a dielectric layer overlying the conducting layer; a metal pad on the dielectric layer, wherein the metal pad, the dielectric layer, and the conducting layer form a capacitor for coupling ESD voltage to the P-well region when an ESD stress is present at the pad; a first N-type heavily-doped region in the P-well region, coupled to the pad; a second N-type heavily-doped region for coupling to a circuit ground of the internal circuit, the second N-type heavily doped region being disposed in the P-well region, spaced apart from and electrically isolated from the first N-type heavily-doped region; a gate structure, disposed on the P-well region between the first N-type heavily-doped region and the second N-type heavily-doped region, for connection to the circuit ground, wherein the first N-type heavily-doped region, the second N-type heavily-doped region, the gate structure, and the P-well region form an NMOS transistor which bypasses ESD stress when an ESD voltage is coupled to the P-well region through the capacitor; and a load connected between the contact region and the circuit ground when the gate structure and the second N-type heavily doped region are connected to the circuit ground, for coupling the P-well region of the NMOS transistor to the circuit ground.