Low voltage device in a high voltage substrate

Claim 1

A semiconductor structure including: a semiconductor substrate of a first conductivity type; a well structure of a second conductivity type formed in said substrate; a first MOS transistor in said well including spaced-apart first transistor source and drain regions of said first conductivity type in said well forming a first transistor channel region therebetween, a first transistor gate disposed above said first transistor channel region and separated therefrom by a first transistor gate dielectric having a first thickness, such that said first transistor can safely operate at a first gate-to-source voltage; a second transistor in said well including spaced-apart second source and drain regions of said first conductivity type in said well forming a second transistor channel therebetween, a second transistor gate disposed above said second transistor channel region and separated therefrom by a second transistor gate dielectric having a second thickness which is greater than the thickness of said first transistor gate dielectric, such that said second transistor can operate at a second gate-to-source voltage, said second gate-to-source voltage having a magnitude sufficient to destroy said first transistor; a first contact diffusion of said second conductivity type located at the edge of said well closest to said first transistor, connected to a voltage source having a magnitude selected to form a depletion layer at the surface of said well sufficient to limit the voltage across said first transistor gate dielectric to approximately the gate-to-source voltage of said first transistor; a second contact diffusion of said second conductivity type located at the edge of said well closest to said second transistor, connected to said voltage source; and said well maintained at a voltage potential equal to at least the voltage potential of any of said first and second source and drain regions in said well.