Semiconductor memory device

Claim 2

A non-volatile semiconductor memory device comprising: (a) a semiconductor substrate of a first conductivity type having a surface portion; (b) memory cells formed in the surface portion of said substrate, said memory cells being divided into a certain number of cell groups, each of said memory cells comprising, first and second semiconductor layers having the first conductivity type serving as a source and a drain of said memory cell, respectively, and first and second conductive layers insulatively provided above said substrate and serving as a floating gate electrode and a control gate electrode of said memory cell, respectively; (c) semiconductors well regions of a second conductivity type formed in the surface portion of said substrate to surround said cell groups respectively; (d) well-potential controller means for applying, when a specific cell group is selected from among said memory cell groups, to said well regions of the remaining cell groups a bias voltage which changes a threshold level of said memory cell to prevent a flow of an ON current between said source and said drain, thereby inhibiting reading and writing of information in the memory cells of said remaining cell groups.

Claim 3

The device according to claim 1, wherein said well-potential controller means supplies the well region of said specific cell group with a voltage having the same polarity as that of the voltage applied to one of said source and said drain of said memory cells included in said specific cell group.

Claim 4

The device according to claim 2, wherein said well-potential controller means comprises: a heavily-doped diffusion layer of the second conductivity type formed in a corresponding one of said well regions; and a third conductive layer electrically connected to said diffusion layer and serving as a well-potential control electrode.

Claim 5

The device according to claim 3, wherein, in a partial information rewrite mode of said device, said third conductive layer applies to a corresponding well region of said remaining cell groups a voltage having a polarity opposite to that of the voltage applied to said source of said memory cell.

Claim 6

The device according to claim 4, wherein said first and second conductive layers are stacked together above said substrate.

Claim 7

The device according to claim 4, wherein said first and second conductive layers are arranged in alignment with each other above said substrate.

Claim 8

The device according to claim 4, wherein a single memory cell is formed in each of said well regions.

Claim 9

The device according to claim 4, wherein a plurality of memory cells are formed in each of said well regions.

Claim 10

The device according to claim 8, wherein said well-potential controller means applies, in the partial information rewrite mode, the bias voltage to said remaining well regions, thereby inhibiting reading and writing of information in said memory cells in said remaining well regions.

Claim 11

An erasable programmable read-only memory device in which information can be erased by radiating ultraviolet rays, comprising: (a) a semiconductive substrate of a first conductivity type; (b) first and second semiconductive well regions of a second conductivity type formed in said substrate; (c) memory cells formed in said first and second well regions, each of said memory cells comprising a metal-insulator-semiconductor field effect transistor which has, first and second semiconductor layers having the first conductivity type and respectively serving as a source and a drain of said transistor, and first and second gate electrodes insulatively provided above said substrate and serving as a floating gate electrode and a control gate electrode of said memory cell; and (d) well-potential controller means, electrically connected to said first and second well regions, for independently controlling, when information stored in said memory cell in said first well region is to be rewritten, a potential of said first well region so as to inhibit reading and writing of the information in said memory cell in said first well region, and for separately controlling a potential of said second well region so as to allow writing of new information in said memory cell in said second well region, whereby said memory cell in said second well region becomes active in place of said memory cell in said first well region and stores the new information, which can be subjected to a following data read operation, and said memory cell in said first well region becomes inactive thereafter, so that the stored information of said memory cell in said first well region can be effectively rewritten without partially erasing data of said memory device.

Claim 12

An erasable programmable read-only memory device in which information can be erased by radiating ultraviolet rays, comprising: (a) a semiconductive substrate of a first conductivity type; (b) first and second semiconductive well regions of a second conductivity type formed in said substrate; (c) memory cells formed in said first and second well regions, each of said memory cells comprising a metal-insulator-semiconductor field effect transistor which has, first and second semiconductor layers having the first conductivity type and respectively serving as a source and a drain of said transistor, and first and second gate electrodes insulatively provided above said substrate and serving as a floating gate electrode and a control gate electrode of said memory cell; and (d) well-potential controller means, electrically connected to said first and second well regions, for independently controlling, when information stored in said memory cell in said first well region is to be rewritten, a potential of said first well region so as to inhibit reading and writing of the information in said memory cell in said first well region, and for separately controlling a potential of said second well region so as to allow writing of new information in said memory cell in said second well region, whereby said memory cell in said second well region becomes active in place of said memory cell in said first well region and stores the new information, which can be subjected to a following data read operation, and said memory cell in said first well region becomes inactive thereafter, so that the stored information of said memory cell in said first well region can be effectively rewritten without partially erasing data of said memory device.

Claim 13

The device according to claim 10, wherein, when information stored in said memory cell in said first well region is to be rewritten, said well-potential controller means applies to said first well region a bias voltage which changes a threshold level of said memory cell in said first well region and prevent a flow of an ON current between said source and said drain, thereby inhibiting reading and writing of information of said memory cell in said first well region, said well-potential controller means setting a potential of said second well region substantially at the same level as that of a potential of one of said source and drain of said memory cell formed in said second well region, thereby allowing writing of new information in said memory cell in said second well region.

Claim 14

The device according to claim 11, wherein said well-potential controller means comprises: first and second heavily-doped semiconductor diffusion layers having the second conductivity type formed in said first and second well regions, respectively.

Claim 15

The device according to claim 12, wherein each of said first and second semiconductive well regions has a plurality of memory cells.

Claim 16

The device according to claim 13, wherein said well-potential controller means applies, when information stored in said memory cells in said first well region is to be rewritten, the bias voltage to said first well region, thereby inhibiting reading and writing of information in said memory cells in said first well region.

Claim 17

The device according to claim 14, wherein said floating gate and said control gate are stacked together above said substrate.

Claim 18

The device according to claim 14, wherein said floating gate and said control gate are arranged in alignment with each other above said substrate.