US4829350A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrostatic discharge integrated circuit protection
Assignee: National Semiconductor Corp
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Filing: 1988-05-05
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Granted: 1989-05-09
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Expires: 2008-05-05
Abstract
Abstract A circuit and structure intended for use in CMOS IC designs acts to protect signal lines against ESD. An array of three transistors is connected so that the voltage pulse that appears on the signal line as a result of ESD, forces at least one transistor into conduction. The circuit responds equally to positive and negative pulses and is, therefore, symmetrical, and independent of bias or supply potentials. In the absence of an ESD pulse the circuit draws a very low leakage current and, therefore, has very little effect upon normal IC operation.
Inventors
- 👤 Bernard D. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:37
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
115 words
A semiconductor integrated circuit having first, second and third MOS transistors formed in a common substrate and each having individual source, drain and gate electrodes, said MOS transistors being interconnected to provide electrostatic discharge protection between a signal line and a common reference line, said interconnection comprising: means commonly connecting said signal line, the gate and drain of said first MOS transistor, the source of said second transistor and the gate of said third transistor; means commonly connecting said reference line, the sources of said first and third MOS transistors and the drain and gate of said second MOS transistor; and means for connecting the drain of said third MOS transistor to said common substrate.
Claim 2
Dependent Claim
115 words
A semiconductor integrated circuit having first, second and third MOS transistors formed in a common substrate and each having individual source, drain and gate electrodes, said MOS transistors being interconnected to provide electrostatic discharge protection between a signal line and a common reference line, said interconnection comprising: means commonly connecting said signal line, the gate and drain of said first MOS transistor, the source of said second transistor and the gate of said third transistor; means commonly connecting said reference line, the sources of said first and third MOS transistors and the drain and gate of said second MOS transistor; and means for connecting the drain of said third MOS transistor to said common substrate.
Claim 3
Dependent Claim
26 words
The integrated circuit of claim 1 wherein said first, second and third MOS transistors are N channel CMOS devices fabricated into a common P well substrate.
Claim 4
Dependent Claim
26 words
The integrated circuit of claim 1 wherein said first, second and third MOS transistors are P channel CMOS devices fabricated into a common N well substrate.
Claim 5
Dependent Claim
58 words
The integrated circuit of claim 1 wherein a thick field oxide is provided over areas of said integrated circuit other than where said transistors are formed, and wherein said first, second and third MOS transistors each have a gate electrode located upon a gate oxide having a thickness approximately equal to that of the integrated circuit field oxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-08 | 1992-11-07 | 1993-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-08 | 1996-11-07 | 1997-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-08 | 2000-11-07 | 2001-05-09 | $7700.00 | Window Closed / Lapsed |