Patent US5677212A successfully refreshed from Google Patents.
US5677212A
Expired / Lapsed
US
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Method of forming a liquid crystal device
Assignee: Seiko Epson Corp
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Filing: 1995-05-31
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Granted: 1997-10-14
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Expires: 2015-05-31
Abstract
Abstract An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.
Inventors
- 👤 Toshiyuki Misawa
- 👤 Hiroyuki Oshima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:33
CPC Classifications
G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13454; H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; G09; G09G; G09G3/00; G09G3/001; G09G3/002; G09G3/003; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3648; G09G3/3674; G09G3/3677; G09G3/3685; G09G3/3688; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D86/00; H10D86/40; H10D86/441; H10D86/60; H10W; H10W20/00; H10W20/40; G02F1/133345; G02F1/136; G02F1/1362; G02F1/136213; G02F1/136254; G09G2300/00; G09G2300/04; G09G2300/0404; G09G2300/0408; G09G2300/08; G09G2300/0809; G09G2330/00; G09G2330/12; G09G3/006; G09G3/2007; G09G3/2011; G09G3/3659; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10W72/00; H10W72/01; H10W72/015; H10W72/01515; H10W72/071; H10W72/075; Y; Y10; Y10S; Y10S257/00; Y10S257/923; Y10S345/00; Y10S345/904
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
198 words
A method of forming a liquid crystal device for an electro-optical device, wherein a substrate has a pixel region and at least one driving means, said pixel region including first thin film transistors through which data signals are supplied to liquid crystal cells, said driving means including at least a shift register having CMOS thin film transistors, said CMOS thin film transistors including second thin film transistors and third thin film transistors, the method comprising: forming first, second and third thin silicon film patterns on the substrate to form first, second and third thin film transistors; forming a gate insulating film on the first, second and third thin silicon film patterns; forming first, second and third gate electrodes on the first, second and third thin silicon film patterns, respectively; implanting first conductivity type impurities to the first, second and third thin silicon film patterns covering the first and second thin film transistors with a masking material and implanting impurities of a second conductivity type opposite to the first conductivity type impurities to the third thin silicon film patterns, wherein a concentration of the second conductivity type impurities is greater than a concentration of the first conductivity type impurities.
Claim 2
Independent Claim
198 words
A method of forming a liquid crystal device for an electro-optical device, wherein a substrate has a pixel region and at least one driving means, said pixel region including first thin film transistors through which data signals are supplied to liquid crystal cells, said driving means including at least a shift register having CMOS thin film transistors, said CMOS thin film transistors including second thin film transistors and third thin film transistors, the method comprising: forming first, second and third thin silicon film patterns on the substrate to form first, second and third thin film transistors; forming a gate insulating film on the first, second and third thin silicon film patterns; forming first, second and third gate electrodes on the first, second and third thin silicon film patterns, respectively; implanting first conductivity type impurities to the first, second and third thin silicon film patterns covering the first and second thin film transistors with a masking material and implanting impurities of a second conductivity type opposite to the first conductivity type impurities to the third thin silicon film patterns, wherein a concentration of the second conductivity type impurities is greater than a concentration of the first conductivity type impurities.
Claim 3
Dependent Claim
23 words
The method of claim 1, wherein the first conductivity type impurities are donor impurities and the second conductivity type impurities are acceptor impurities.
Claim 4
Dependent Claim
22 words
The method of claim 1, wherein the first conductivity type impurities are acceptor impurities and the second conductivity impurities are donor impurities.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-13 | 2001-04-14 | 2001-10-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-13 | 2005-04-14 | 2005-10-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-13 | 2009-04-14 | 2009-10-14 | $7700.00 | Window Closed / Lapsed |