US5341012A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS device for use in connection with an active matrix panel
Assignee: Seiko Epson Corp
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Filing: 1992-07-31
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Granted: 1994-08-23
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Expires: 2012-07-31
Abstract
Abstract An active matrix panel including a matrix of driving electrodes couples through thin film transistor switches to a corresponding source line and gate line and at least one of a driver circuit including complementary thin film transistors for driving the source and/or gate lines of the picture elements on the substrate. The thin film transistors of the active matrix have the same cross-sectional structure as the P-type or the N-type thin film transistors forming the driver circuit and are formed during the same patterning process.
Inventors
- 👤 Toshiyuki Misawa
- 👤 Hiroyuki Oshima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:31
CPC Classifications
G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13454; H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; G09; G09G; G09G3/00; G09G3/001; G09G3/002; G09G3/003; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3648; G09G3/3674; G09G3/3677; G09G3/3685; G09G3/3688; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D86/00; H10D86/40; H10D86/441; H10D86/60; H10W; H10W20/00; H10W20/40; G02F1/133345; G02F1/136; G02F1/1362; G02F1/136213; G02F1/136254; G09G2300/00; G09G2300/04; G09G2300/0404; G09G2300/0408; G09G2300/08; G09G2300/0809; G09G2330/00; G09G2330/12; G09G3/006; G09G3/2007; G09G3/2011; G09G3/3659; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10W72/00; H10W72/01; H10W72/015; H10W72/01515; H10W72/071; H10W72/075; Y; Y10; Y10S; Y10S257/00; Y10S257/923; Y10S345/00; Y10S345/904
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
110 words
A CMOS device, comprising: a substrate; a thin silicon film carried by said substrate; a thin film transistor formed from said thin silicon film, and carried by the substrate, said thin film transistor having a source region and a drain region formed from at least a first type of impurity; and a second transistor, formed from said thin silicon film, and carried by the substrate, said second transistor having a source region and a drain region formed from at least said first type of impurity and a second type of impurity; wherein the concentrations of the first type of impurity and second type of impurity are different from each other.
Claim 2
Dependent Claim
110 words
A CMOS device, comprising: a substrate; a thin silicon film carried by said substrate; a thin film transistor formed from said thin silicon film, and carried by the substrate, said thin film transistor having a source region and a drain region formed from at least a first type of impurity; and a second transistor, formed from said thin silicon film, and carried by the substrate, said second transistor having a source region and a drain region formed from at least said first type of impurity and a second type of impurity; wherein the concentrations of the first type of impurity and second type of impurity are different from each other.
Claim 3
Dependent Claim
65 words
The CMOS device of claim 1, wherein the thin film transistor is a P-type having source and drain regions formed from at least acceptor impurities and the second transistor is an N-type having source and drain regions formed from at least donor impurities, the concentration of donor impurities in the second transistor being greater than the concentration of acceptor impurities in the thin film transistor.
Claim 4
Dependent Claim
65 words
The CMOS device of claim 1, wherein the thin film transistor is an N-type having source and drain regions formed from at least donor impurities and the second transistor is a P-type having source and drain regions formed from at least acceptor impurities, the concentration of acceptor impurities in the second transistor being greater than the concentration of donor impurities in the thin film transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |