EP0239958A2
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Thin film semiconductor device and method of manufacturing the same
Assignee: Hitachi Ltd
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Filing: 1987-03-27
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Granted: —
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Expires: 2007-03-27
Abstract
Abstract Complementary thin film transistors (C-TFT) formed on an insulating substrate, comprising a pair of highly resistive n-type silicon islands (2, 20), a pair of heavily doped n-type regions (12, 13) formed on one (2) of the islands to form source and drain regions of n-channel TFT, a pair of contacts (170, 180) formed on the surface of the other island (20) and establishing a high potential barrier when the underlying region is of n-type and a low potential barrier when the underlying region is inverted to be of p-type. The process for manufacturing complementary TFTs can be simplified significantly.
Inventors
- 👤 Nobutake Konishi
- 👤 Yoshikazu Hosokawa
- 👤 Akio Mimura
- 👤 Takaya Suzuki
- 👤 Jun-Ichi Ohwada
- 👤 Hideaki Kawakami
- 👤 Kenji Miyata
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 22:51
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/40; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D64/00; H10D64/60; H10D64/64; H10D64/647; H10D86/01; H10D86/021; H10D86/60; G02F2202/00; G02F2202/10; G02F2202/103; G02F2202/104
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
239 words
A complementary thin film semiconductor device comprising: an insulating underlie (1) for supporting the semiconductor device to be formed thereon; a pair of thin film semiconductor island regions (2, 20; 21, 210) supported on said insulating underlie, spaced from each other and having a high resistivity and a conductivity type of i- or n-type; a pair of heavily doped n-type regions (12, 13; 23, 24) formed on one (2; 21) of said island regions and spaced from each other by a predetermined distance, the heavily doped regions constituting a source and a drain region of an n-channel thin film transistor (n-TFT) and the predetermined distance defining a channel length of the n-TFT; a first pair of metal contacts (170, 180; 29, 30) formed on a surface of the other (20; 210) of said island regions and spaced from each other by another predetermined distance, the metal contact forming a high potential barrier when the underlying semiconductor region is of n-type and a reduced potential barrier when the underlying region is of p-type, the pair of metal contacts constituting a source and a drain region of a p-channel thin film transistor (p-TFT) and said another predetermined distance defining a channel length of the p-TFT; and a pair of insulated gate structures (14, 15; 140, 150; 19, 20; 190, 20) formed on said pair of island regions, each at a position between the source and the drain of the associated TFT.
Claim 2
Dependent Claim
239 words
A complementary thin film semiconductor device comprising: an insulating underlie (1) for supporting the semiconductor device to be formed thereon; a pair of thin film semiconductor island regions (2, 20; 21, 210) supported on said insulating underlie, spaced from each other and having a high resistivity and a conductivity type of i- or n-type; a pair of heavily doped n-type regions (12, 13; 23, 24) formed on one (2; 21) of said island regions and spaced from each other by a predetermined distance, the heavily doped regions constituting a source and a drain region of an n-channel thin film transistor (n-TFT) and the predetermined distance defining a channel length of the n-TFT; a first pair of metal contacts (170, 180; 29, 30) formed on a surface of the other (20; 210) of said island regions and spaced from each other by another predetermined distance, the metal contact forming a high potential barrier when the underlying semiconductor region is of n-type and a reduced potential barrier when the underlying region is of p-type, the pair of metal contacts constituting a source and a drain region of a p-channel thin film transistor (p-TFT) and said another predetermined distance defining a channel length of the p-TFT; and a pair of insulated gate structures (14, 15; 140, 150; 19, 20; 190, 20) formed on said pair of island regions, each at a position between the source and the drain of the associated TFT.
Claim 3
Dependent Claim
52 words
A complementary thin film semiconductor device according to claim 1, wherein said semiconductor is silicon of polycrystalline, micro-crystalline or amorphous state, and said metal contact (170, 180; 29, 30) is formed of one selected from the group consisting of Ti, Ta, Cr, Mo, Pd, Pt, W, their silicides and the mixtures thereof.
Claim 4
Dependent Claim
42 words
A complementary thin film semiconductor device according to claim 1, wherein said insulated gate structure (14, 15; 140, 150) and said source and drain regions (12, 13; 170, 180) are all disposed on a same side of the island region (2; 20).
Claim 5
Dependent Claim
52 words
A complementary thin film semiconductor device according to claim 1, wherein said insulated gate structure (19, 20; 190, 20) is disposed between said insulating underlie (1) and said island region (21; 210), and said source and drain regions (23, 24; 29, 30) are disposed on the other side of the island region.
Claim 6
Dependent Claim
55 words
A complementary thin film semiconductor device according to claim 1, further comprising a second pair of metal contacts (17, 18; 27, 28) formed on said pair of heavily doped n-type regions (12, 13; 23, 24) and formed substantially of the same material as that of said first pair of metal contacts (170, 180; 29, 30).
Claim 7
Dependent Claim
25 words
A complementary thin film semiconductor device according to claim 1, further comprising a conductive wiring pattern (10-1) connecting the source regions of n-TFT and p-TFT.
Claim 8
Dependent Claim
33 words
A complementary thin film semiconductor device according to claim 6, further comprising another conductive wiring pattern (10-2) connecting an input signal line with said insulated gate structures, thereby forming a complementary TFT inverter.
Claim 9
Dependent Claim
22 words
A complementary thin film semiconductor device according to claim 1, wherein said insulating underlie (1) is a transparent substrate carrying transparent electrodes.
Claim 10
Dependent Claim
21 words
A complementary thin film semiconductor device according to claim 8, further comprising a liquid crystal display associated with said transparent electrodes.
Claim 11
Dependent Claim
24 words
A complementary thin film semiconductor device according to claim 9, wherein said TFTs constitute a circuit (340, 350) for driving said liquid crystal display.
Claim 12
Independent Claim
169 words
A method of manufacturing a complementary thin film semiconductor device comprising the steps of: depositing a pair of thin film island regions (2, 20; 21, 210) on an insulating underlie member (1), said island regions being formed of a high resistivity semiconductor of i- or n-type; forming a pair of heavily doped n-type regions (12, 13; 23, 24) on one (2; 21) of said island regions, the heavily doped n-type regions spaced from each other by a predetermined distance and serving as a source and a drain; forming a pair of metal contacts (170, 180; 29, 30) on the other (20; 210) of said island regions, the contacts forming a high potential barrier when the underlying semiconductor is of n-type and a reduced potential barrier when the underlying semiconductor is of p-type, and serving as a source and a drain; and forming an insulated gate structure (14, 15; 140, 150; 19, 20; 190, 20) on each of said island regions at a position between the source and the drain.
Claim 13
Independent Claim
169 words
A method of manufacturing a complementary thin film semiconductor device comprising the steps of: depositing a pair of thin film island regions (2, 20; 21, 210) on an insulating underlie member (1), said island regions being formed of a high resistivity semiconductor of i- or n-type; forming a pair of heavily doped n-type regions (12, 13; 23, 24) on one (2; 21) of said island regions, the heavily doped n-type regions spaced from each other by a predetermined distance and serving as a source and a drain; forming a pair of metal contacts (170, 180; 29, 30) on the other (20; 210) of said island regions, the contacts forming a high potential barrier when the underlying semiconductor is of n-type and a reduced potential barrier when the underlying semiconductor is of p-type, and serving as a source and a drain; and forming an insulated gate structure (14, 15; 140, 150; 19, 20; 190, 20) on each of said island regions at a position between the source and the drain.
Claim 14
Dependent Claim
60 words
A method of manufacturing a complementary thin film semiconductor device according to claim 11, wherein said step of forming a pair of metal contacts (170, 180; 29, 30) follows said step of forming a pair of heavily doped regions (12, 13; 23, 24) and also forms a pair of metal contacts (17, 18; 27, 28) on said heavily doped regions.
Claim 15
Dependent Claim
68 words
A method of manufacturing a complementary thin film semiconductor device according to claim 11, wherein said step of forming a pair of metal contacts (170, 180; 29, 30) includes depositing a metal layer (16; 26) on the thin film island regions (2, 20; 21, 210), which metal is one selected from the group consisting of Ti, Ta, Cr, Mo, Pd, Pt, W, their silicides and the mixtures thereof.
Claim 16
Dependent Claim
58 words
A method of manufacturing a complementary thin film semiconductor device according to claim 11, wherein said step of forming a pair of metal contacts (170, 180; 29, 30) includes depositing a metal layer (16; 26) at least on the other (20; 210) of said thin film island regions (2, 20; 21, 210) and thermally treating the deposited layer.
Claim 17
Dependent Claim
71 words
A method of manufacturing a complementary thin film semiconductor device according to claim 12, wherein the semiconductor is silicon, and the step of forming a pair of metal contacts (170, 180; 29, 30) includes depositing a metal layer (16; 26) made of one selected from the group consisting of Mo, Pt, W, and the mixtures thereof and thermally treating the deposited layer to allow reaction of the deposited metal with silicon.
Claim 18
Dependent Claim
38 words
A method of manufacturing a complementary thin film semiconductor device according to claim 15, wherein the thickness of the deposited metal layer (16; 26) is smaller than the thickness of said heavily doped regions (12, 13; 23, 24).
References Cited (Backward Citations)
No citation records indexed.
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