Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
191 words
A method of making a complementary insulated gate field effect transistor integrated circuit by including the steps of: forming on a surface of a semiconductor layer of a first conductivity type a dielectric layer; forming on said dielectric layer a polycrystalline support layer; forming on an exposed surface of said semiconductor layer a first insulating layer having a first aperture therein; forming a lightly doped tub region of a second conductivity type through said first aperture and a second insulating layer thereon, said tub region extending through said semiconductor layer to said dielectric layer; forming first source and drain regions defining a channel of a first field effect transistor in said lightly doped tub region and second source and drain regions defining a channel of a second field effect transistor in said semiconductor layer, said source and drain regions extending to the exposed surface of said semiconductor layer and lightly doped tub region; and forming first and second gate electrodes spaced by a gate insulation layer on the exposed surface of said lightly doped tub region and semiconductor layer from the channels of said first and second field effect transistors, respectively.
Claim 2
Independent Claim
191 words
A method of making a complementary insulated gate field effect transistor integrated circuit by including the steps of: forming on a surface of a semiconductor layer of a first conductivity type a dielectric layer; forming on said dielectric layer a polycrystalline support layer; forming on an exposed surface of said semiconductor layer a first insulating layer having a first aperture therein; forming a lightly doped tub region of a second conductivity type through said first aperture and a second insulating layer thereon, said tub region extending through said semiconductor layer to said dielectric layer; forming first source and drain regions defining a channel of a first field effect transistor in said lightly doped tub region and second source and drain regions defining a channel of a second field effect transistor in said semiconductor layer, said source and drain regions extending to the exposed surface of said semiconductor layer and lightly doped tub region; and forming first and second gate electrodes spaced by a gate insulation layer on the exposed surface of said lightly doped tub region and semiconductor layer from the channels of said first and second field effect transistors, respectively.
Claim 3
Dependent Claim
21 words
The method of claim 1 in which the gate electrodes are formed prior to formation of the source and drain electrodes.
Claim 4
Dependent Claim
56 words
The method of claim 2 in which the gate insulation layer comprises a composite of silicon oxide and silicon nitride, the gate electrode comprises polycrystalline silicon, and the source and drain electrodes of said first and second field effect transistors extend through said lightly doped tub region and said semiconductor layer, respectively, to said dielectric layer.
Claim 5
Dependent Claim
23 words
The method of claim 3 additionally comprising the step of reducing the thickness of said semiconductor layer after forming said polycrystalline support layer.
Claim 6
Dependent Claim
20 words
The method of claim 1 in which the gate electrodes are formed after formation of the source and drain electrodes.
Claim 7
Dependent Claim
49 words
The method of claim 5 additionally comprising the step of reducing the thickness of said semiconductor layer after forming said polycrystalline support layer and in which the source and drain electrodes of said first and second transistors extend through said lightly doped tub region and said semiconductor layer, respectively.
Claim 8
Dependent Claim
52 words
The method of claim 1 in which said lightly doped tub region is formed by diffusing a P-type impurity in said semiconductor layer through the exposed surface, driving in the diffused impurity, and removing a portion of said semiconductor layer from the exposed surface to reduce the thickness of said semiconductor layer.