High density semiconductor circuit using CMOS transistors

Claim 2

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means; an n-channel MOS transistor device circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first n-channel MOS transistor whose current path is connected at one end of said circuit point, and a plurality of second n-channel MOS transistors whose current paths are connected in parallel between the other end of the current path said first n-channel MOS transistor and said first terminal; and a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said circuit point and said second terminal, said p- and n-channel MOS transistors both being enhancement types, said p-channel MOS circuit having a first p-channel MOS transistor which is connected between said circuit point and said second terminal and a plurality of second p-channel MOS transistors whose current paths are series-connected between said circuit point and said second terminal; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 3

A semiconductor integrated circuit according to claim 1, wherein said input means includes a plurality of input terminals, and a gate of said first n-channel MOS transistor is connected to a gate of said first p-channel MOS transistor and to one of said input terminals, and gates of said second n-channel MOS transistors are connected to respective gates of said second p-channel MOS transistors and to the remaining ones of said input terminals.

Claim 4

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means; an n-channel MOS transistor device circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first switching n-channel MOS transistor whose current path is connected between said circuit point and said first output terminal, and a second switching n-channel MOS transistor and a plurality of n-channel MOS transistors whose current paths are series-connected between said first output terminal and said first terminal; and a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said circuit point and said second terminal, said p- and n-channel MOS transistors both being enhancement types, said p-channel MOS circuit having a first switching p-channel MOS transistor whose current path is connected between said circuit point and said second output terminal, a second switching p-channel MOS transistor and a plurality of p-channel MOS transistors whose current paths are series-connected between said second output terminal and said second terminal; and gatof said first and second switching n-channel MOS transistors are respectively connected to gates of said first and second switching p-channel MOS transistors; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 5

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means; an n-channel MOS transistor device circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first switching n-channel MOS transistor whose current path is connected between said circuit point and said first output terminal, and a second switching n-channel MOS transistor and a plurality of n-channel MOS transistors whose current paths are series-connected between said first output terminal and said first terminal; and a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said circuit point and said second terminal, said p- and n-channel MOS transistors both being enhancement types, said p-channel MOS circuit having a first switching p-channel MOS transistor whose current path is connected between said circuit point and said second output terminal, a second switching p-channel MOS transistor and a plurality of p-channel MOS transistors whose current paths are series-connected between said second output terminal and said second terminal; and gatof said first and second switching n-channel MOS transistors are respectively connected to gates of said first and second switching p-channel MOS transistors; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 6

A semiconductor integrated circuit according to claim 3, wherein said first terminal, said second terminal and said circuit point are a positive power source terminal, a negative power source terminal and a ground terminal, respectively.

Claim 7

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means; an n-channel MOS circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first n-channel MOS transistor whose current path is connected at one end to said circuit point, and a plurality of second n-channel MOS transistors whose current paths are connected in parallel between the other end of the current path of said first n-channel MOS transistor and said first terminal; and a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected between said circuit point and said second terminal, said p- and n-channel MOS transistors both being depletion types; said p-channel MOS circuit having a first p-channel MOS transistor which is connected between said circuit point and said second terminal and a plurality of second p-channel MOS transistors whose current paths are series-connected between said circuit point and said second terminal; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 8

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means; an n-channel MOS circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first n-channel MOS transistor whose current path is connected at one end to said circuit point, and a plurality of second n-channel MOS transistors whose current paths are connected in parallel between the other end of the current path of said first n-channel MOS transistor and said first terminal; and a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected between said circuit point and said second terminal, said p- and n-channel MOS transistors both being depletion types; said p-channel MOS circuit having a first p-channel MOS transistor which is connected between said circuit point and said second terminal and a plurality of second p-channel MOS transistors whose current paths are series-connected between said circuit point and said second terminal; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 9

A semiconductor integrated circuit according to claim 5, wherein said input means includes plurality of input terminals, and a gate of said first n-channel MOS transistor is connected to a gate of said first p-channel MOS transistor and to one of said input terminals, and gates of said second n-channel MOS transistors are connected to respective gates of said second p-channel MOS transistors and to the remaining ones of said input terminals.

Claim 10

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means; said output means including first and second output terminals, an n-channel MOS circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first switching n-channel MOS transistor whose current path is connected between said circuit point and said first output terminal, and a second switching n-channel MOS transistor and a plurality of n-channel MOS transistors whose current paths are series-connected between said first output terminal and said first terminal; a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected between said circuit point and said second terminal, said p- and n-channel MOS transistors both being depletion types; said p-channel MOS circuit having a first switching p-channel MOS transistor whose current path is connected between said circuit point and said second output terminal, a second switching p-channel MOS transistor, and a plurality of p-channel MOS transistors whose current paths are series-connected between said second output terminal and said second terminal; gates of said first and second switching n-channel MOS transistors being respectively connected to gates of said first and second switching p-channel MOS transistors; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 11

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means; said output means including first and second output terminals, an n-channel MOS circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first switching n-channel MOS transistor whose current path is connected between said circuit point and said first output terminal, and a second switching n-channel MOS transistor and a plurality of n-channel MOS transistors whose current paths are series-connected between said first output terminal and said first terminal; a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected between said circuit point and said second terminal, said p- and n-channel MOS transistors both being depletion types; said p-channel MOS circuit having a first switching p-channel MOS transistor whose current path is connected between said circuit point and said second output terminal, a second switching p-channel MOS transistor, and a plurality of p-channel MOS transistors whose current paths are series-connected between said second output terminal and said second terminal; gates of said first and second switching n-channel MOS transistors being respectively connected to gates of said first and second switching p-channel MOS transistors; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 12

A semiconductor integrated circuit according to claim 7, wherein aid first terminal, said second terminal and said circuit point are a positive power source terminal, a negative power source terminal and a ground terminal, respectively.

Claim 13

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means; an n-channel MOS circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first switching n-channel MOS transistor whose current path is connected between said circuit point, and a plurality of second n-channel MOS transistors whose current paths are connected in parallel between the other end of the current path of said first n-channel MOS transistor and said first terminal; a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said circuit point and said second terminal, said p-and n-channel MOS transistors having a zero threshold; said p-channel MOS circuit having a firsts p-channel MOS transistor which is connected between said circuit point and said second terminal and a plurality of second p-channel MOS transistors whose current paths are series-connected between said circuit point and said terminal; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 14

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means; an n-channel MOS circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first switching n-channel MOS transistor whose current path is connected between said circuit point, and a plurality of second n-channel MOS transistors whose current paths are connected in parallel between the other end of the current path of said first n-channel MOS transistor and said first terminal; a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said circuit point and said second terminal, said p-and n-channel MOS transistors having a zero threshold; said p-channel MOS circuit having a firsts p-channel MOS transistor which is connected between said circuit point and said second terminal and a plurality of second p-channel MOS transistors whose current paths are series-connected between said circuit point and said terminal; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 15

A semiconductor integrated circuit according to claim 9, wherein said input means includes a plurality of input terminals, and a gate of said first n-channel MOS transistor is connected to a gate of said first p-channel MOS transistor and to one of said input terminals, and gates of second n-channel MOS transistors are connected to respective gates of said second p-channel MOS transistors and to the remaining ones of said input terminals.

Claim 16

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means, said output means including first and second output terminals; an n-channel MOS circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first switching n-channel MOS transistor whose current path is connected between said circuit point and said first output terminal, and a second switching n-channel MOS transistor and a plurality of n-channel MOS transistors whose current paths are series-connected between said first output terminal and said first terminal; and a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said circuit point and said second terminal, said p- and n-channel MOS transistors having a zero threshold; said p-channel MOS circuit having a first switching p-channel MOS transistor whose current path is connected between said circuit point and said second output terminal, a second switching p-channel MOS transistor and a plurality of p-channel MOS transistors whose current paths are series-connected between said second output terminal and said second terminal; gates of said first and second switching n-channel MOS transistors being respectively connected to gates of said first and second switching p-channel MOS transistors; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 17

A semiconductor integrated circuit comprising: a first terminal set at a first potential; a second terminal set at a second potential more negative than said first potential; input and output means, said output means including first and second output terminals; an n-channel MOS circuit including at least one n-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said first terminal and a circuit point which is coupled to said output means, said n-channel MOS circuit having a first switching n-channel MOS transistor whose current path is connected between said circuit point and said first output terminal, and a second switching n-channel MOS transistor and a plurality of n-channel MOS transistors whose current paths are series-connected between said first output terminal and said first terminal; and a p-channel MOS circuit including at least one p-channel MOS transistor whose gate is connected to said input means and whose current path is connected between said circuit point and said second terminal, said p- and n-channel MOS transistors having a zero threshold; said p-channel MOS circuit having a first switching p-channel MOS transistor whose current path is connected between said circuit point and said second output terminal, a second switching p-channel MOS transistor and a plurality of p-channel MOS transistors whose current paths are series-connected between said second output terminal and said second terminal; gates of said first and second switching n-channel MOS transistors being respectively connected to gates of said first and second switching p-channel MOS transistors; wherein the conduction state of said n-channel MOS transistor and said p-channel MOS transistor is controlled in response to an input signal supplied through said input means to set a potential at said circuit point in accordance with the conduction states of said n-channel MOS transistor and said p-channel MOS transistor.

Claim 18

A semiconductor integrated circuit according to claim 11, wherein said first terminal, said second terminal and said circuit point are a positive power source terminal, a negative power source terminal and a ground terminal, respectively.

Claim 19

A semiconductor circuit comprising: a circuit point to be set at a predetermined potential, first and second terminals to be respectively set at higher and lower potentials than the predetermined potential, first and second output terminals, a first switching p-channel MOS transistor whose current path is connected between said circuit point and first output terminal, a first switching n-channel MOS transistor and a plurality of n-channel MOS transistors whose current paths are serially connected between said first terminal and first output terminal, a second switching n-channel MOS transistor whose gate is connected to a gate of said first p-channel MOS transistor and whose current path is connected between said circuit point and second output terminal, a second switching p-channel MOS transistor and a plurality of p-channel MOS transistors whose current paths are serially connected between said second terminal and second output terminal, said second switching p-channel MOS transistor having a gate connected to a gate of said first switching n-channel MOS transistor.

Claim 20

A semiconductor circuit comprising: a circuit point to be set at a predetermined potential, first and second terminals to be respectively set at higher and lower potentials than the predetermined potential, first and second output terminals, a first switching p-channel MOS transistor whose current path is connected between said circuit point and first output terminal, a first switching n-channel MOS transistor and a plurality of n-channel MOS transistors whose current paths are serially connected between said first terminal and first output terminal, a second switching n-channel MOS transistor whose gate is connected to a gate of said first p-channel MOS transistor and whose current path is connected between said circuit point and second output terminal, a second switching p-channel MOS transistor and a plurality of p-channel MOS transistors whose current paths are serially connected between said second terminal and second output terminal, said second switching p-channel MOS transistor having a gate connected to a gate of said first switching n-channel MOS transistor.