Complementary MOS transistors without an isolation region

Claim 2

A complementary metal-oxide-semiconductor (MOS) transistor comprising one of a semiconductor substrate and a semiconductor region provided on an insulating substrate, which includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type formed adjacent to said first semiconductor region; a third semiconductor region of the second conductivity type provided on said first semiconductor region; a fourth semiconductor region of the first conductivity type provided on said second semiconductor region; a first channel region formed between said first semiconductor region and said fourth semiconductor region and having a subregion with a prescribed conductivity type having a specified impurity concentration; a second channel region formed between said second semiconductor region and said third semiconductor region and having a subregion with a prescribed conductivity type having a specified impurity concentration; a fifth semiconductor region of the second conductivity type provided in a portion of said first channel region and adjacent to the subregion of said second channel region; a sixth semiconductor region of the first conductivity type formed in a portion of said second channel region and adjacent to the subregion of said first channel region; and gate electrode means positioned above said first and second channel regions through an insulation layer for controlling said first and second channel regions; an MOS transistor of the first channel type of said complementary MOS transistor including said fourth semiconductor region, the subregion of said first channel region and said sixth semiconductor region; an MOS transistor of the second channel type of said complementary MOS transistor including said third semiconductor region, the subregion of said second channel region and said fifth semiconductor region.

Claim 3

The complementary MOS transistor according to claim 1, which is of the depletion-depletion type, in which said first conductivity type is the P type; said second conductivity type is the N type; said third region is of the N type and is doped with an impurity at a high concentration; said fourth region is of the P type and is doped with an impurity at a high concentration; first channel region includes a P type subregion doped with an impurity at a lower concentration, and a fifth N type region doped with an impurity at a concentration intermediate between the concentrations at which said third region and said subregion of the second channel region are doped with an impurity; and said second channel region includes an N type subregion doped with an impurity at a low concentration and a sixth P type region doped with an impurity intermediate between the concentrations at which said fourth region and said subregion of the first channel region are doped with an impurity.

Claim 4

The complementary MOS transistor according to claim 1, which is of the enhancement-enhancement type, in which said first conductivity type is the P type; said second conductivity type is the N type; said third region is of the N type and is doped with an impurity at a high concentration; said fourth region is of the P type and is doped with an impurity at a high concentration; said first channel region includes an N type subregion doped with an impurity at a low concentration and a fifth N type region doped with an impurity at a concentration intermediate between the concentrations at which said third region and the subregion of said first channel region are doped with an impurity; and said second channel region includes a P type subregion doped with an impurity at a low concentration and a sixth P type region doped with an impurity at a concentration intermediate between the concentrations at which the fourth region and the subregion of said second channel region are doped with an impurity.

Claim 5

The complementary MOS transistors according to claim 1, wherein the gate electrode means includes a common gate electrode formed above said first and second channel regions through an insulation layer.

Claim 6

The complementary MOS transistors according to claim 1, wherein the gate electrode means includes a common floating gate electrode embedded in an insulation layer formed on said first and second channel regions; and a common outermost gate electrode provided on said insulation layer.

Claim 7

The complementary MOS transistors according to claim 1, wherein the gate electrode means includes a first electrode provided above said first channel region through an insulation layer and supplied with a first gate signal, and a second electrode fromed above said second channel region through an insulation layer and supplied with a second gate signal; and said first and second electrodes are formed of semiconductor elements with the opposite conductivity types, and are arranged in an integral form.

Claim 8

The complementary MOS transistors according to claim 1, wherein said fourth region is formed in said second region, said second region being connected to said first power source through a region of the second conductivity type which is doped with an impurity at a concentration higher than that at which the fourth region is doped with an impurity; said third region is formed in said first region, said first region being connected to said second power source through a region of a first conductivity type which is doped with an impurity at a concentration higher than that at which said first region is doped with an impurity; said gate electrode means includes a common electrode placed above said first and second channel regions through an insulation layer, said common gate electrode being connected to an input terminal; and said third and fourth regions are connected to a common output terminal.

Claim 9

The complementary MOS transistors according to claim 1, wherein a first MOS transistor is formed on said first region, which includes said third region, a seventh semiconductor region of the second conductivity type which is formed on said first region and doped with an impurity substantially at the same concentration as that at which said third region is doped with an impurity, and an eighth region provided between said third and seventh regions and doped with an impurity at a concentration lower than that at which the seventh region is doped with an impurity; a second MOS transistor is constituted on said first region, which includes said third region, a ninth semiconductor region of the second conductivity type which is formed on said first region and doped with an impurity at a concentration substantially the same as that at which said third region is doped with an impurity, and said first region lying between said third and ninth regions; a gate electrode positioned above said first and second channel region through an insulation layer is connected to said third region; the gate electrode of said first MOS transistor is connected to said first region; said fourth semiconductor region is connected to said seventh semiconductor region; the gate electrode of said second MOS transistor is connected to a word line; said ninth region is connected to a bit line; said second region is connected to a first power source; and said first region is connected to a second power source.

Claim 10

A semiconductor memory device, which comprises a first metal-oxide-semiconductor (MOS) transistor of a second channel type, one terminal of which is connected to a first power source; a third MOS transistor of a first channel type, one terminal of which is connected to a second power source; a second MOS transistor of a second channel type which is connected between the other terminal of said first MOS transistor and the other terminal of said third MOS transistor; and a fourth MOS transistor which is connected between the junction of said first and second MOS transistors and a bit line and whose gate electrode is connected to a word line, and in which the gate electrodes of said first and third MOS transistors are connected to the junction of said first and second MOS transistors and the gate electrode of said second MOS transistor is connected to said second power source, and wherein said first and third MOS transistors are made into a complementary MOS transistor without an isolation region between said two MOS transistors, said complementary MOS transistor comprising a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type which is set adjacent to said first region; a third region of the second conductivity type which is formed on said first region; a fourth region of the first conductivity type which is formed on said second region; a first channel region formed between said first region and fourth region and having a subregion with a prescribed conductivity type having a specified impurity concentration; a second channel region formed between said second region and third region and having a subregion with a prescribed conductivity type having a specified concentration; a fifth region of the second conductivity type provided in a portion of said first channel region and adjacent to the subregion of said second channel region; a sixth region of the first conductivity type formed in a portion of said second channel region and adjacent to the subregion of said first channel region; and gate electrode means provided above said first and second channel regions through an insulation layer for controlling said first and second channel regions; an MOS transistor of the first channel type of said complementary MOS transistor including said fourth region, the subregion of said first channel region and said sixth region; an MOS transistor of the second channel type of said complementary MOS transistor including said third region, the subregion of said second channel region and said fifth region.

Claim 11

A semiconductor memory device, which comprises a first metal-oxide-semiconductor (MOS) transistor of a second channel type, one terminal of which is connected to a first power source; a third MOS transistor of a first channel type, one terminal of which is connected to a second power source; a second MOS transistor of a second channel type which is connected between the other terminal of said first MOS transistor and the other terminal of said third MOS transistor; and a fourth MOS transistor which is connected between the junction of said first and second MOS transistors and a bit line and whose gate electrode is connected to a word line, and in which the gate electrodes of said first and third MOS transistors are connected to the junction of said first and second MOS transistors and the gate electrode of said second MOS transistor is connected to said second power source, and wherein said first and third MOS transistors are made into a complementary MOS transistor without an isolation region between said two MOS transistors, said complementary MOS transistor comprising a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type which is set adjacent to said first region; a third region of the second conductivity type which is formed on said first region; a fourth region of the first conductivity type which is formed on said second region; a first channel region formed between said first region and fourth region and having a subregion with a prescribed conductivity type having a specified impurity concentration; a second channel region formed between said second region and third region and having a subregion with a prescribed conductivity type having a specified concentration; a fifth region of the second conductivity type provided in a portion of said first channel region and adjacent to the subregion of said second channel region; a sixth region of the first conductivity type formed in a portion of said second channel region and adjacent to the subregion of said first channel region; and gate electrode means provided above said first and second channel regions through an insulation layer for controlling said first and second channel regions; an MOS transistor of the first channel type of said complementary MOS transistor including said fourth region, the subregion of said first channel region and said sixth region; an MOS transistor of the second channel type of said complementary MOS transistor including said third region, the subregion of said second channel region and said fifth region.

Claim 12

The semiconductor memory device according to claim 9, wherein said second MOS transistor includes said third region, a seventh region of the second conductivity type which is formed in said first region and an eighth region of the second conductivity type which is formed in said first region between said third and seventh regions and is doped with an impurity at a specified concentration; and said fourth MOS transistor includes said third region, a ninth region of the second conductivity type which is formed on said first region, and a tenth region having the same conductivity type and impurity concentration as said first region lying between said third and ninth regions.