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US5656553A
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Method for forming a monolithic electronic module by dicing wafer stacks
Assignee: International Business Machines Corp
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Filing: 1996-05-30
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Granted: 1997-08-12
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Expires: 2016-05-30
Abstract
Abstract A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.
Inventors
- 👤 James Marc Leas
- 👤 Steven Howard Voldman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:33
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10W; H10W90/00; H10W72/00; H10W72/834; H10W90/20
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
79 words
A method for forming an electronic module comprising the steps of: (a) providing a plurality of wafers, each wafer having at least one planar array of multiple chips which has a peripheral shape; (b) forming a wafer stack by stacking the plurality of wafers so that the at least one planar array of multiple chips of each wafer having the predefined peripheral shape align within the wafer stack; and (c) dicing the wafer stack along the predefined peripheral shape.
Claim 2
Independent Claim
79 words
A method for forming an electronic module comprising the steps of: (a) providing a plurality of wafers, each wafer having at least one planar array of multiple chips which has a peripheral shape; (b) forming a wafer stack by stacking the plurality of wafers so that the at least one planar array of multiple chips of each wafer having the predefined peripheral shape align within the wafer stack; and (c) dicing the wafer stack along the predefined peripheral shape.
Claim 3
Dependent Claim
83 words
The method of claim 1, wherein each planar array of multiple chips having the peripheral shape has an edge along said predefined peripheral shape, and wherein said method further comprises prior to said step (b) forming for each chip transfer metal connections to the edge defined along the predefined peripheral shape, and wherein said step (b) includes stacking the plurality of wafers so that the edges of the planar arrays of multiple chips containing transfer metal thereto within said wafer stack are aligned.
Claim 4
Dependent Claim
54 words
The method of claim 2, wherein after said dicing step (c), the edges of the planar arrays of multiple chips are aligned and form a common face of the electronic module, and wherein said method further comprises providing metallization on said common face to facilitate electrical connection to the chips in the electronic module.
Claim 5
Dependent Claim
23 words
The method of claim 3, wherein said providing of metallization includes providing contact pads electrically connected to transfer metals at said common face.
Claim 6
Dependent Claim
34 words
The method of claim 4, wherein said providing of metallization further comprises providing interconnect wiring on said common face to electrically interconnect chips of different planar arrays of chips disposed within the electronic module.
Claim 7
Dependent Claim
31 words
The method of claim 5, further comprising dicing the electronic module into multiple sub-modules, each sub-module comprising a plurality of chip layers, each chip layer containing at least one chip therein.
Claim 8
Dependent Claim
45 words
The method of claim 1, wherein the planar arrays of multiple chips define a common face of the electronic module subsequent to said dicing step (c), and wherein said method further comprises providing interconnect metallization on said common face subsequent to said dicing step (c).
Claim 9
Dependent Claim
51 words
The method of claim 7, further comprising dicing the electronic module into electronic sub-modules, each electronic sub-module comprising a plurality of chip layers which are at least partially interconnected by said interconnect metallization applied to the common face of the electronic module prior to said dicing thereof into said electronic sub-modules.
Claim 10
Dependent Claim
67 words
The method of claim 1, wherein each planar array of multiple chips comprises a plurality of integrated circuit (IC) chips, said IC chips having transfer wiring to a common edge disposed along said peripheral shape, and wherein said forming step (b) includes stacking the plurality of wafers such that the common edges of the planar arrays of multiple chips in different wafers align within the wafer stack.
Claim 11
Dependent Claim
84 words
The method of claim 1, wherein the predefined peripheral shape of each planar array of multiple chips comprises a non-square rectangular shape such that each planar array of chips comprises a bar-shaped planar array, and wherein said forming step (b) comprises stacking the plurality of wafers so that the bar-shaped planar arrays of different chips align within the wafer stack, and said dicing step (c) comprises dicing the wafer stack along the predefined peripheral shape such that the electronic module has two parallel edges.
Claim 12
Dependent Claim
73 words
The method of claim 1, wherein said providing step (a) includes providing the plurality of wafers such that each wafer has a plurality of bar-shaped planar arrays defined therein, said plurality of bar-shaped planar arrays being disposed identically in each wafer of the plurality of wafers, and wherein said dicing step (c) comprises dicing the wafer stack along the bar-shaped planar arrays in the wafer stack such that multiple electronic modules are formed.
Claim 13
Dependent Claim
38 words
The method of claim 11, wherein said dicing of said electronic module comprises dicing said electronic module such that each electronic sub-module formed has a plurality of chip layers with each chip layer having only one chip therein.
Claim 14
Dependent Claim
22 words
The method of claim 1, wherein said forming step (b) includes bonding the plurality of wafers together to form said wafer stack.
Claim 15
Dependent Claim
21 words
The method of claim 1, further comprising prior to said forming step (b), thinning each wafer of said plurality of wafers.
Claim 16
Dependent Claim
38 words
The method of claim 1, wherein said providing step (a) comprises testing each wafer for functionality and selecting only wafers for said forming step (b) having functional chips within said at least one planar array of multiple chips.
Claim 17
Dependent Claim
45 words
The method of claim 1, wherein each planar array of multiple chips having the peripheral shape has two opposing edges along said predefined peripheral shape, and wherein said step (c) includes dicing the wafer stack along the two opposing edges of the predefined peripheral shape.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |