Patent US5654243A successfully refreshed from Google Patents.
US5654243A
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Process for fabricating a semiconductor device in a resin package housed in a frame having high conductivity
Assignee: Fujitsu Ltd
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Filing: 1996-08-14
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Granted: 1997-08-05
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Expires: 2016-08-14
Abstract
Abstract A semiconductor device including a substrate, solder bumps provided on a lower major surface of the substrate, a semiconductor chip provided on an upper major surface of the substrate, a resin package body provided on the upper major surface of the substrate so as to bury the semiconductor chip therein, a thermally conductive frame member having a flange part supporting the substrate of a rim part of the substrate, wherein the thermal conductive frame member has a thermal conductivity substantially larger than that of the resin package body and extending along to and in an intimate contact with side walls of the resin package body.
Inventors
- 👤 Yoshiyuki Yoneda
- 👤 Kazuto Tsuji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 04:15
CPC Classifications
H; H10; H10W; H10W76/00; H10W76/40; H10W76/42; H10W76/47; H10W40/00; H10W40/20; H10W40/22; H10W40/70; H10W40/77; H10W40/778; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/00; H10W90/701; H05; H05K; H05K1/00; H05K1/02; H05K1/0201; H05K3/00; H05K3/30; H05K3/303; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H10W72/00; H10W72/50; H10W72/541; H10W72/5445; H10W72/851; H10W72/874; H10W72/884; H10W90/731; H10W90/734; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144; Y10T29/49146
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
96 words
A method for fabricating a semiconductor device, comprising the steps of: mounting a semiconductor chip carrying solder bumps on a lower major surface thereon, on a substrate surrounded by an edge, such that said substrate carries said semiconductor chip thereon; providing a frame member such that said frame member surrounds said edge of said substrate, said frame member thereby defining a space on said substrate such that said space includes said semiconductor chip; and filling said space with a resin; wherein said frame member has a thermal conductivity greater than a thermal conductivity of said resin.
Claim 2
Independent Claim
96 words
A method for fabricating a semiconductor device, comprising the steps of: mounting a semiconductor chip carrying solder bumps on a lower major surface thereon, on a substrate surrounded by an edge, such that said substrate carries said semiconductor chip thereon; providing a frame member such that said frame member surrounds said edge of said substrate, said frame member thereby defining a space on said substrate such that said space includes said semiconductor chip; and filling said space with a resin; wherein said frame member has a thermal conductivity greater than a thermal conductivity of said resin.
Claim 3
Independent Claim
177 words
A method for fabricating a semiconductor device, comprising the steps of: forming an integral substrate frame such that said integral substrate includes a main frame and a plurality of substrates connected to said main frame by respective arm portions to form an integral body, such that each of said plurality of substrates has a peripheral edge surrounding said substrate except for said arm portion; mounting a plurality of semiconductor chips on respective substrates forming a part of said integral substrate frame; mounting said integral substrate frame in a die that holds therein a plurality of frame members in correspondence to said plurality of substrates, such that each of said substrates is held in a corresponding frame in a state that said frame engages with said peripheral edge of said substrate, said frame thereby defining a space on said substrate; filling a resin on said space in each of said substrates, such that said resin buries said semiconductor chip held on said substrate underneath; and cutting said arm portions for separating each of said substrates from each other.
Claim 4
Independent Claim
177 words
A method for fabricating a semiconductor device, comprising the steps of: forming an integral substrate frame such that said integral substrate includes a main frame and a plurality of substrates connected to said main frame by respective arm portions to form an integral body, such that each of said plurality of substrates has a peripheral edge surrounding said substrate except for said arm portion; mounting a plurality of semiconductor chips on respective substrates forming a part of said integral substrate frame; mounting said integral substrate frame in a die that holds therein a plurality of frame members in correspondence to said plurality of substrates, such that each of said substrates is held in a corresponding frame in a state that said frame engages with said peripheral edge of said substrate, said frame thereby defining a space on said substrate; filling a resin on said space in each of said substrates, such that said resin buries said semiconductor chip held on said substrate underneath; and cutting said arm portions for separating each of said substrates from each other.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |