Patent US5654204A successfully refreshed from Google Patents.
US5654204A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Die sorter
Assignee: Advantest Singapore Pte Ltd
•
Filing: 1994-07-20
•
Granted: 1997-08-05
•
Expires: 2014-07-20
Abstract
Abstract An integrated circuit probing method and apparatus therefor. The apparatus includes a main system controller coupled to a network interface, graphic user interface, and equipment interface. A high speed bus connects the main system controller to a group of subsystems. The subsystems includes subsystems such as input cassettes, input frame handing, frame to align, die align, die probing, die bin and die output, output cassettes subsystem, among others. The integrated circuit probing apparatus allows for probing of each individual die through the die probing subsystem, typically a high speed subsystem.
Inventors
- 👤 James C. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:16
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; G; G01; G01R; G01R31/00; G01R31/01; G01R31/28; G01R31/282; G01R31/2831
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
52 words
A method of manufacture for a semiconductor integrated circuit comprising the steps of: providing a fabricated wafer comprising a plurality of semiconductor integrated circuits, said plurality of semiconductor integrated circuits being substantially untested; separating each of said semiconductor integrated circuits from said fabricated wafer; and probing each of said semiconductor integrated circuits.
Claim 2
Independent Claim
52 words
A method of manufacture for a semiconductor integrated circuit comprising the steps of: providing a fabricated wafer comprising a plurality of semiconductor integrated circuits, said plurality of semiconductor integrated circuits being substantially untested; separating each of said semiconductor integrated circuits from said fabricated wafer; and probing each of said semiconductor integrated circuits.
Claim 3
Dependent Claim
17 words
The method of claim 1 further comprising the step of testing each of said semiconductor integrated circuits.
Claim 4
Dependent Claim
21 words
The method of claim 2 further comprising the step of assembling each of said semiconductor integrated circuits after said testing step.
Claim 5
Dependent Claim
25 words
The method of claim 1 further comprising the step of aligning each of said semiconductor integrated circuits to an interface means before said probing step.
Claim 6
Dependent Claim
15 words
The method of claim 4 wherein said interface means comprises a probe card comprising probes.
Claim 7
Dependent Claim
23 words
The method of claim 4 wherein said aligning step comprises a pre-aligning step and a fine alignment step of said semiconductor integrated circuit.
Claim 8
Dependent Claim
13 words
The method of claim 1 wherein said separating step comprises a sawing step.
Claim 9
Dependent Claim
18 words
The method of claim 2 further comprising a step of categorizing each of said tested semiconductor integrated circuits.
Claim 10
Dependent Claim
33 words
The method of claim 8 wherein said categorizing step separates each of said semiconductor integrated circuits into die binning group consisting essentially of a fast die, a slow die, and a reject die.
Claim 11
Dependent Claim
21 words
The method of claim 8 further comprising a step of placing each of said categorized semiconductor integrated circuits onto separate frames.
Claim 12
Independent Claim
24 words
A method of manufacture for a semiconductor integrated circuit comprising the step of testing a semiconductor integrated circuit by use of a die sorter.
Claim 13
Independent Claim
24 words
A method of manufacture for a semiconductor integrated circuit comprising the step of testing a semiconductor integrated circuit by use of a die sorter.
Claim 14
Dependent Claim
28 words
The method of claim 11 wherein said testing step comprises a step of probing said semiconductor integrated circuit, said semiconductor integrated circuit being separated from a semiconductor wafer.
Claim 15
Dependent Claim
29 words
The method of claim 11 further comprising a step of: separating said semiconductor integrated circuit from a semiconductor wafer; and providing said semiconductor integrated circuit to said die sorter.
Claim 16
Dependent Claim
15 words
The method of claim 11 further comprising a step of assembling and semiconductor integrated circuit.
Claim 17
Independent Claim
57 words
A method of identifying integrated circuits on a fabricated semiconductor wafer comprising the steps of: providing a fabricated wafer comprising a plurality of semiconductor integrated circuits onto a wafer saw, said plurality of semiconductor integrated circuits being untested; and entering information comprising an identification characteristic of said fabricated wafer into a memory coupled to said wafer saw.
Claim 18
Independent Claim
57 words
A method of identifying integrated circuits on a fabricated semiconductor wafer comprising the steps of: providing a fabricated wafer comprising a plurality of semiconductor integrated circuits onto a wafer saw, said plurality of semiconductor integrated circuits being untested; and entering information comprising an identification characteristic of said fabricated wafer into a memory coupled to said wafer saw.
Claim 19
Dependent Claim
25 words
The method of claim 15 further comprising a step of retrieving said information of said fabricated wafer from a computer network before said entering step.
Claim 20
Dependent Claim
15 words
The method of claim 15 wherein said memory comprises a memory of said wafer saw.
Claim 21
Dependent Claim
14 words
The method of claim 15 wherein said memory comprises a touch boat memory device.
Claim 22
Dependent Claim
17 words
The method of claim 15 wherein said retrieving step occurs through manual data entry and network capability.
Claim 23
Dependent Claim
11 words
The method of claim 15 wherein said information comprises wafer identification.
Claim 24
Dependent Claim
32 words
The method of claim 20 wherein said wafer identification can be selected from a group of information consisting essentially from a planarization characteristic, a device size, test results, and a product name.
Claim 25
Dependent Claim
33 words
The method of claim 15 further comprising a step of entering said information of said fabricated wafer from a group of interface means consisting essentially of a keyboard, a bar-code, and keyboard/bar-code combination.
Claim 26
Dependent Claim
49 words
The method of claim 15 further comprising a step of: sawing said fabricated wafer to separate each of said semiconductor integrated circuits; recognizing a wafer pattern from said semiconductor integrated circuit; storing said wafer pattern on a memory means; and retrieving said wafer pattern at a die prober apparatus.
Claim 27
Dependent Claim
20 words
The method of claim 23 further comprising a step of using said wafer pattern to align said semiconductor integrated circuit.
Claim 28
Independent Claim
84 words
A method of set-up for a probe card comprising the steps of: providing a pin array carrier assembly comprising a pin array top surface at a test site; adjusting said pin array carrier assembly to contact said pin array top surface with probes of a probe card; sending first signals to each of said probes; receiving second signals through said pin array top surface; decoding said second signals; identifying an X-coordinate, Y-coordinate, and THETA-coordinate of each of said probes through said decoded second signals.
Claim 29
Independent Claim
84 words
A method of set-up for a probe card comprising the steps of: providing a pin array carrier assembly comprising a pin array top surface at a test site; adjusting said pin array carrier assembly to contact said pin array top surface with probes of a probe card; sending first signals to each of said probes; receiving second signals through said pin array top surface; decoding said second signals; identifying an X-coordinate, Y-coordinate, and THETA-coordinate of each of said probes through said decoded second signals.
Claim 30
Dependent Claim
14 words
The method of claim 25 wherein said pin array comprising a plurality of pins.
Claim 31
Dependent Claim
23 words
The method of claim 25 further comprising a step of adjusting said THETA-coordinate of said probe card by reference to a known standard.
Claim 32
Independent Claim
57 words
A method of manufacture for a semiconductor integrated circuit comprising the steps of: providing a fabricated wafer comprising a plurality of semiconductor integrated circuits, said plurality of semiconductor integrated circuits being untested; separating each of said semiconductor integrated circuits from said fabricated wafer; and probing each of said semiconductor integrated circuits, said semiconductor integrated circuits being unpackaged.
Claim 33
Independent Claim
57 words
A method of manufacture for a semiconductor integrated circuit comprising the steps of: providing a fabricated wafer comprising a plurality of semiconductor integrated circuits, said plurality of semiconductor integrated circuits being untested; separating each of said semiconductor integrated circuits from said fabricated wafer; and probing each of said semiconductor integrated circuits, said semiconductor integrated circuits being unpackaged.
Claim 34
Independent Claim
58 words
A method of identifying integrated circuits on a fabricated semiconductor wafer comprising the steps of: providing a fabricated wafer comprising a plurality of semiconductor integrated circuits onto a wafer saw, said fabricated wafer being substantially free from electrical tests; and entering information comprising an identification characteristic of said fabricated wafer into a memory coupled to said wafer saw.
Claim 35
Independent Claim
58 words
A method of identifying integrated circuits on a fabricated semiconductor wafer comprising the steps of: providing a fabricated wafer comprising a plurality of semiconductor integrated circuits onto a wafer saw, said fabricated wafer being substantially free from electrical tests; and entering information comprising an identification characteristic of said fabricated wafer into a memory coupled to said wafer saw.
References Cited (Backward Citations)
US4816422A
Cited
JPS63232319A
Cited
US4814296A
Cited
US4967229A
Cited
US5105255A
Cited
US5314844A
Cited
US5206181A
Cited
US5369060A
Cited
US5393706A
Cited
US5396068A
Cited
US5360747A
Cited
US5326428A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |