Method and apparatus for transferring data in a storage device including a dual-port buffer

Claim 1

A data storage subsystem, comprising: a processor interface for coupling said data storage subsystem to a computer processor; a redundant array of storage units for redundantly storing data, such that said redundant array provides protection against a loss of data; a storage unit interface; a subsystem processor for controlling operation of said data storage subsystem; a dual-port buffer memory having a first port for serially transferring data between said dual-port buffer memory and said processor interface, and having a second port for transferring data between said dual-port buffer memory and said storage unit interface; wherein data transfers by said first and second ports are allowed to be concurrent and are controlled by said subsystem processor; wherein data transfers by said first and second ports are substantially independent of each other; wherein data exits said dual-port buffer memory in the order that data enters said dual-port buffer memory, such that locations at which data is stored within said dual-port buffer memory need not be addressed; first, second, third, and fourth bus branches; first, second, and third bus switches controlled by said subsystem processor; a first series connection comprising said first bus branch, said first bus switch, and said second bus branch interconnecting said first port of said dual-port buffer memory and said processor interface; a second series connection comprising said first bus branch, said second bus switch and, and said third bus branch interconnecting said system processor and said processor interface; a third series connection comprising said third bus branch, said third bus switch, and said fourth bus branch interconnecting said system processor and said storage unit interface; and a fourth connection comprising said fourth bus branch interconnecting said storage unit interface and said second port of said dual-port buffer memory.

Claim 9

A method ensuring that data does not cross the same data bus twice when data is written from a computer processor to a redundant array of storage units, or when data is read from said redundant array of storage units, the method comprising the steps of: providing a processor interface that is coupled to said computer processor by way of a data bus; providing a redundant array of storage units for redundantly storing data, such that protection is provided against loss of data; providing a storage unit interface; providing a subsystem processor; providing a dual-port buffer memory having a first port for serially transferring data between said dual-port buffer memory and said processor interface, and having a second port for transferring data between said dual-port buffer memory and said storage unit interface; wherein data transfers through said first and second ports are allowed to be concurrent and are controlled by said subsystem processor; wherein data transfers through said first and second ports are substantially independent of each other; wherein data exits said dual-port buffer memory in the order that data enters said dual-port buffer memory, such that locations at which data is stored within said dual-port buffer memory need not be addressed; providing first, second, third, and fourth data bus branches; providing first, second, and third bus switches that are controlled by said subsystem processor; providing a first series connection comprising said first data bus branch, said first bus switch, and said second data bus branch interconnecting said first port of said dual-port buffer memory and said processor interface; providing a second series connection comprising said first data bus branch, said second bus switch and, and said third data bus branch interconnecting said system processor and said processor interface; providing a third series connection comprising said third data bus branch, said third bus switch, and said fourth data bus branch interconnecting said system processor and said storage unit interface; and providing a fourth connection comprising said fourth data bus branch interconnecting said storage unit interface and said second port of said dual-port buffer memory.

Claim 10

A method ensuring that data does not cross the same data bus twice when data is written from a computer processor to a redundant array of storage units, or when data is read from said redundant array of storage units, the method comprising the steps of: providing a processor interface that is coupled to said computer processor by way of a data bus; providing a redundant array of storage units for redundantly storing data, such that protection is provided against loss of data; providing a storage unit interface; providing a subsystem processor; providing a dual-port buffer memory having a first port for serially transferring data between said dual-port buffer memory and said processor interface, and having a second port for transferring data between said dual-port buffer memory and said storage unit interface; wherein data transfers through said first and second ports are allowed to be concurrent and are controlled by said subsystem processor; wherein data transfers through said first and second ports are substantially independent of each other; wherein data exits said dual-port buffer memory in the order that data enters said dual-port buffer memory, such that locations at which data is stored within said dual-port buffer memory need not be addressed; providing first, second, third, and fourth data bus branches; providing first, second, and third bus switches that are controlled by said subsystem processor; providing a first series connection comprising said first data bus branch, said first bus switch, and said second data bus branch interconnecting said first port of said dual-port buffer memory and said processor interface; providing a second series connection comprising said first data bus branch, said second bus switch and, and said third data bus branch interconnecting said system processor and said processor interface; providing a third series connection comprising said third data bus branch, said third bus switch, and said fourth data bus branch interconnecting said system processor and said storage unit interface; and providing a fourth connection comprising said fourth data bus branch interconnecting said storage unit interface and said second port of said dual-port buffer memory.