Dual port memory system

Claim 2

A dual port memory system comprising: a memory for storing m data bytes at each addressable location therein; an n byte wide first data bus and a p byte wide second data bus, wherein n<m and p<m; m, byte wide, parallel, first write registers connected between said first bus and said memory; m, byte wide, parallel, first read registers connected in parallel with said first write registers between said first bus and said memory; m, byte wide, parallel, second write registers connected between said second bus and said memory; and m, byte wide, parallel, second read registers connected in parallel with said write registers between said second bus and said memory.

Claim 3

The system of claim 1 further comprising: first and second address lines, n first control lines, and p second control lines; wherein every first write register is connected to said first address line, each first register is connected to one of said first control lines with an equal number of said first write registers being connected to each first control line, every second write register is connected to said second address line, and each second write register is connected to one of said second control lines with an equal number of said second write registers being connected to each second control line.

Claim 4

The system of claim 2 wherein said address lines and control lines provide signals which selectively enable said write registers to receive one or more data bytes from the connected bus.

Claim 5

The system of claim 1 further comprising: m multiplexers connected between said memory and first and second write registers; wherein said multiplexers are responsive to control signals for selectively enabling the transfer of up to m data bytes from said first or second write registers into said memory.

Claim 6

The system of claim 1 further comprising: first and second control lines; wherein every first read register is connected to said first control line and every second read register is connected to said second control line; and wherein said first and second control lines provide complementary enable signals, respectively, and a clock signal.

Claim 7

The system of claim 5 wherein said first or second read registers respond to said enable and clock signals to receive m data bytes from said memory.

Claim 8

The system of claim 1 further comprising: n first multiplexers and p second multiplexers connected between said first and second read registers and first and second busses, respectively; wherein each first read register is connected to one of said first multiplexers with an equal number of said first read registers being connected to each of said first multiplexers; and wherein each second read register is connected to one of said second multiplexers with an equal number of said second read registers being connected to each of said second multiplexers.

Claim 9

The system of claim 7 further comprising: first and second address lines; wherein each of said first multiplexers is connected to said first address line and each of said second multiplexers is connected to said second address line; and wherein said address lines provide signals to said multiplexers to transfer predetermined data bytes from said read registers to said bus.

Claim 10

The system of claim 1 wherein n=p.

Claim 11

The system of claim 1 wherein n and p are integer factors of m.

Claim 12

A dual port memory system comprising: a memory for storing m data bytes at each addressable location therein; an n byte wide first data bus and a p byte wide second data bus, wherein n<m and p<m; m, byte wide, parallel, first write registers connected between said first bus and said memory; m, byte wide, parallel, first read registers connected in parallel with said first write registers between said first bus and said memory; m, byte wide, parallel, second write registers connected between said second bus and said memory; m, byte wide, parallel, second read registers connected in parallel with said write registers between said second bus and said memory; first and second address lines, n first control lines, and p second control lines; m first multiplexers connected between said memory and first and second write registers; third and fourth control lines; and n second multiplexers and p third multiplexers connected between said first and second read registers and first and second busses, respectively; wherein every first write register is connected to said first address line, each first register is connected to one of said first control lines with an equal number of said first write registers being connected to each first control line, every second write register is connected to said second address line, and each second write register is connected to one of said second control lines with an equal number of said second write registers being connected to each second control line; wherein said first multiplexers are responsive to control signals for selectively enabling the transfer of up to m data bytes from said first or second write registers into said memory; wherein every first read register is connected to said third control line and every second read register is connected to said fourth control line; wherein said third and fourth control lines provide complementary enable signals, respectively, and a clock signal; wherein each first read register is connected to one of said second multiplexers with an equal number of said first read registers being connected to each of said second multiplexers; and wherein each second read register is connected to one of said third multiplexers with an equal number of said second read registers being connected to each of said third multiplexers.

Claim 13

A dual port memory system comprising: a memory for storing m data bytes at each addressable location therein; an n byte wide first data bus and a p byte wide second data bus, wherein n<m and p<m; m, byte wide, parallel, first write registers connected between said first bus and said memory; m, byte wide, parallel, first read registers connected in parallel with said first write registers between said first bus and said memory; m, byte wide, parallel, second write registers connected between said second bus and said memory; m, byte wide, parallel, second read registers connected in parallel with said write registers between said second bus and said memory; first and second address lines, n first control lines, and p second control lines; m first multiplexers connected between said memory and first and second write registers; third and fourth control lines; and n second multiplexers and p third multiplexers connected between said first and second read registers and first and second busses, respectively; wherein every first write register is connected to said first address line, each first register is connected to one of said first control lines with an equal number of said first write registers being connected to each first control line, every second write register is connected to said second address line, and each second write register is connected to one of said second control lines with an equal number of said second write registers being connected to each second control line; wherein said first multiplexers are responsive to control signals for selectively enabling the transfer of up to m data bytes from said first or second write registers into said memory; wherein every first read register is connected to said third control line and every second read register is connected to said fourth control line; wherein said third and fourth control lines provide complementary enable signals, respectively, and a clock signal; wherein each first read register is connected to one of said second multiplexers with an equal number of said first read registers being connected to each of said second multiplexers; and wherein each second read register is connected to one of said third multiplexers with an equal number of said second read registers being connected to each of said third multiplexers.

Claim 16

The system of claim 12 wherein data bytes are transferable between said first write or read registers and said first bus concurrently with the transfer of data bytes between said second write or read registers and said second bus.