Dual port memory controller

Claim 2

A dual port memory controller for use in interfacing a pair of processors to a common memory having a plurality of memory banks each organized into row and column defined addresses, said dual port memory controller comprising: RAS means for generating row address strobe signals; CAS means for generating column address strobe signals; refresh means for periodically refreshing said common memory, said refresh means operating upon each of said banks within said common memory in a staggered manner; arbitration means coupled to said pair of processors having logic means for granting either of said processors or said refresh means access to said common memory in accordance with a predetermined priority; and memory cycle sequencing means coupled to said RAS means and said CAS means and said arbitration means for controlling the operation of said RAS means and CAS means upon said common memory.

Claim 3

A dual port memory controller as set forth in claim 1 wherein said arbitration means include means for simultaneously granting access to different ones of said memory banks of said common memory to one of said processors selected in accordance with said predetermined priority and to said refresh means.

Claim 4

A dual port memory controller as set forth in claim 2 wherein said arbitration means include queue means for temporarily storing a processor request and wherein each request for access by said processors is applied simultaneously to said arbitration means and said queue means.

Claim 5

A dual port memory controller as set forth in claim 3 wherein said refresh means includes refresh cycle sequencing means coupled to said RAS means and said CAS means and said arbitration means for controlling the operation of said RAS means and CAS means upon said common memory and wherein said CAS means are operative upon said memory prior to operation of said RAS means upon said memory.

Claim 6

A dual port memory controller as set forth in claim 4 wherein said arbitration means includes means determing the temporary storage of a processor request within said queue means and selecting a predetermined one of said pair of processors for access to said memory in the absence of a stored processor request within said queue means.

Claim 7

A dual port memory controller as set forth in claim 5 wherein said arbitration means include means removing said temporarily stored processor requests from said queue means once access to said common memory of said processor request has been granted.

Claim 8

For use in controlling the access of a first and a second processor to a common memory having a plurality of memory banks each organized into a plurality of row and column defined addresses, a dual port memory controller comprising: RAS means for generating row address strobe signals during memory cycling; CAS means for generating column address strobe signals during memory cycling; an arbitration/port selection control having a logic array for controlling the access to said common memory of said first and second processors in accordance with a predetermined priority; a first port command decode circuit coupled to said first processor and said arbitration means for determing the presence of a memory access request from said first processor and coupling said request to said arbitration means; a second port command decode circuit coupled to said second processor and said arbitration means for determining the presence of a memory access request from said second processor and coupling said request to said arbitration means; queue means for temporarily storing a processor memory access request; a plurality of memory cycle sequencers each coupled to said arbitration means for providing a plurality of timing controls of signals produced by said arbitration means during memory cycles, said memory sequencers applying said column address strobe signals to said common memory prior to application of said row address strobe signals; refresh means coupled to said arbitration means for periodically producing a plurality of memory refresh signals; a refresh cycle sequencer coupled to said refresh means and said common memory for providing a plurality of timing controls of signals produced by said arbitration means during memory refresh cycles said refresh cycle sequencer applying said column address strobe signals to said common memory prior to application of said row address strobe signals; and means providing staggered operation of said refresh means upon said memory banks in said common memory.

Claim 9

For use in controlling the access of a first and a second processor to a common memory having a plurality of memory banks each organized into a plurality of row and column defined addresses, a dual port memory controller comprising: RAS means for generating row address strobe signals during memory cycling; CAS means for generating column address strobe signals during memory cycling; an arbitration/port selection control having a logic array for controlling the access to said common memory of said first and second processors in accordance with a predetermined priority; a first port command decode circuit coupled to said first processor and said arbitration means for determing the presence of a memory access request from said first processor and coupling said request to said arbitration means; a second port command decode circuit coupled to said second processor and said arbitration means for determining the presence of a memory access request from said second processor and coupling said request to said arbitration means; queue means for temporarily storing a processor memory access request; a plurality of memory cycle sequencers each coupled to said arbitration means for providing a plurality of timing controls of signals produced by said arbitration means during memory cycles, said memory sequencers applying said column address strobe signals to said common memory prior to application of said row address strobe signals; refresh means coupled to said arbitration means for periodically producing a plurality of memory refresh signals; a refresh cycle sequencer coupled to said refresh means and said common memory for providing a plurality of timing controls of signals produced by said arbitration means during memory refresh cycles said refresh cycle sequencer applying said column address strobe signals to said common memory prior to application of said row address strobe signals; and means providing staggered operation of said refresh means upon said memory banks in said common memory.

Claim 10

A dual port memory controller as set forth in claim 7 wherein said refresh cycle sequencer and said memory cycle sequencer may be simultaneously operative upon different ones of said plurality of memory banks within said common memory.