US4899342A
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Method and apparatus for operating multi-unit array of memories
Assignee: Thinking Machines Corp
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Filing: 1988-02-01
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Granted: 1990-02-06
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Expires: 2008-02-01
Abstract
Abstract A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and at least one spare read/write memory unit. The ECC circuit generates an error correction code for each block of data to be stored in the system and supplies this code along with the block of data to the memory units for storage. The system further comprises means for generating from a sequence of blocks of data and associated error correction codes retrieved from these memory units a sequence of bits which correct an error in the information retrieved from one memory unit and means for writing this sequence of correction bits to the spare read/write memory unit. Advantageously, the system also comprises means for rewriting the sequence of correction bits to a memory unit after a faulty memory unit has been repaired or replaced. Preferably, the sequence of correction bits is generated by the same ECC circuit which generates the error correction codes; and the sequence of correction bits is connected to the spare memory unit, a repaired unit or a replacement unit through an array of multiplexers.
Inventors
- 👤 David Potter
- 👤 Laurence N. Provost
- 👤 John M. Baron
- 👤 David Stefanovic
- 👤 Eric D. Sharakan
- 👤 David A. Sheppard
- 👤 Marshall A. Isman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
245 words
A multi-unit memory system comprising: an error correction code generation circuit which generates for each block of data to be stored in said memory system an error correction code, each block of data comprising a first plurality of digits and each error correcting code comprising a second plurality of digits from which at least one digit of error may be detected and corrected in the block of data, a plurality of read/write memory units, which store the digits of said blocks of data and associated error correction codes generated by said error correction code generation circuit and read said digits, at least some of the different digits of each code and its associated data block being stored in different memory units, at least one spare read/write memory unit that is similar in operation to an individual read/write memory unit of said plurality of read/write memory units, means for generating from the digits of a block of data and associated error correction code read from said memory units a digit which corrects an error in a digit read from one of said memory units, said generating means operating on a sequence of said blocks of data and associated error correction codes to generate a sequence of correct digits, and means for accessing the spare read/write memory unit to store therein said sequence of correct digits as the sequence of blocks of data and associated error correction codes are read from the plurality of read/write memory units.
Claim 2
Dependent Claim
245 words
A multi-unit memory system comprising: an error correction code generation circuit which generates for each block of data to be stored in said memory system an error correction code, each block of data comprising a first plurality of digits and each error correcting code comprising a second plurality of digits from which at least one digit of error may be detected and corrected in the block of data, a plurality of read/write memory units, which store the digits of said blocks of data and associated error correction codes generated by said error correction code generation circuit and read said digits, at least some of the different digits of each code and its associated data block being stored in different memory units, at least one spare read/write memory unit that is similar in operation to an individual read/write memory unit of said plurality of read/write memory units, means for generating from the digits of a block of data and associated error correction code read from said memory units a digit which corrects an error in a digit read from one of said memory units, said generating means operating on a sequence of said blocks of data and associated error correction codes to generate a sequence of correct digits, and means for accessing the spare read/write memory unit to store therein said sequence of correct digits as the sequence of blocks of data and associated error correction codes are read from the plurality of read/write memory units.
Claim 3
Dependent Claim
58 words
The system of claim 1 further comprising first and second multiplexers, said first multiplexers selectively supplying to said plurality of read/write memory units either blocks of data and error correction codes or said sequence of correct digits of data and said second multiplexers supplying output signals from either said plurality of memory units or said spare memory unit.
Claim 4
Dependent Claim
69 words
The system of claim 2 wherein there are as many first multiplexers and as many second multiplexers as there are memory units in said plurality of read/write memory units, each said first multiplexer supplying one of said plurality of read/write memory units and each of said second multiplexers multiplexing signals from all of said spare memory units and a different one of each of said plurality of memory units.
Claim 5
Dependent Claim
21 words
The system of claim 3 wherein there are thirty-nine read/write memory units in said plurality of memory units and three spares.
Claim 6
Dependent Claim
27 words
The system of claim 1 wherein each digit in a block of data and its associated error correction codes is stored in a different read/write memory unit.
Claim 7
Dependent Claim
21 words
The apparatus of claim 1 wherein each read/write memory unit and each spare read/write memory unit is an identical disk drive.
Claim 8
Independent Claim
220 words
The method of operating a multi-unit memory system comprising the steps of: generating for each block of data to be stored in said memory system an error correction code from which at least one bit of error may be detected and corrected in the block data, each block of data comprising a first plurality of digits and each error correcting code comprising a second plurality of digits, storing in a plurality of read/write memory units the digits of said blocks of data and associated error correction codes, at least some of the different digits of each code and its associated data block being stored in different memory units, generating from the digits of a block of data and associated error correction code read from said memory units a digit which corrects an error in a digit read from one of said memory units, said generating step operating on a sequence of said block of data and associated error correction codes to generate a sequence of correct digits, and storing in a spare read/write memory unit that is similar in operation to one of the read/write memory units of said plurality of read/write memory units said sequence of corrects digits as the sequence of blocks of data and associated error correction codes are read from the plurality of read/write memory units.
Claim 9
Independent Claim
220 words
The method of operating a multi-unit memory system comprising the steps of: generating for each block of data to be stored in said memory system an error correction code from which at least one bit of error may be detected and corrected in the block data, each block of data comprising a first plurality of digits and each error correcting code comprising a second plurality of digits, storing in a plurality of read/write memory units the digits of said blocks of data and associated error correction codes, at least some of the different digits of each code and its associated data block being stored in different memory units, generating from the digits of a block of data and associated error correction code read from said memory units a digit which corrects an error in a digit read from one of said memory units, said generating step operating on a sequence of said block of data and associated error correction codes to generate a sequence of correct digits, and storing in a spare read/write memory unit that is similar in operation to one of the read/write memory units of said plurality of read/write memory units said sequence of corrects digits as the sequence of blocks of data and associated error correction codes are read from the plurality of read/write memory units.
Claim 10
Dependent Claim
84 words
The method of claim 7 further comprising the steps of: repairing or replacing the memory unit from which said error was read, generating from a sequence of blocks of data and associated error correction codes read from said plurality of memory units except for the unit that was repaired or replaced a sequence of digits which recreate information previously stored in the memory unit which was repaired or replaced, and writing on the memory unit that was repaired or replaced said sequence of digits.
Claim 11
Dependent Claim
27 words
The system of claim 7 wherein each digit in a block of data and its associated error correction codes is stored in a different read/write memory unit.
Claim 12
Dependent Claim
21 words
The method of claim 7 wherein each write/read memory unit and each spare read/write memory unit is an identical disk drive.
Claim 13
Dependent Claim
285 words
A multi-unit memory system comprising: an error correction code generation circuit which generates for each block of data to be stored in said memory system an error correction code, each block of data comprising a first plurality of digits and each error correcting code comprising a second plurality of digits from which at least one digit of error may be detected and corrected in the block of data, a plurality of read/write memory units, which store the digits of said blocks of data and associated error correction codes generated by said error correction code generation circuit and read said digits, data being written to said read/write memory units in parallel and being read from said read/write memory units in parallel, each of the different digits of each code and its associated data block being stored at the same address in different memory units, at least one spare read/write memory unit similar in operation to one of the read/write memory units of said plurality of read/write memory units and operating in parallel therewith, means for generating from the digits of a block of data and associated error correction code read from said memory units a digit which corrects a error in a digit read from one of said memory units, said generating means operating on a sequence of said blocks of data and associated error correction codes to generate a sequence of correct digits in place of a sequence of digits read from one of said memory units, and means for accessing the spare read/write memory unit to store therein said sequence of correct digits as the sequence of blocks of data and associated error correction codes are read from the plurality of read/write memory units.
Claim 14
Dependent Claim
285 words
A multi-unit memory system comprising: an error correction code generation circuit which generates for each block of data to be stored in said memory system an error correction code, each block of data comprising a first plurality of digits and each error correcting code comprising a second plurality of digits from which at least one digit of error may be detected and corrected in the block of data, a plurality of read/write memory units, which store the digits of said blocks of data and associated error correction codes generated by said error correction code generation circuit and read said digits, data being written to said read/write memory units in parallel and being read from said read/write memory units in parallel, each of the different digits of each code and its associated data block being stored at the same address in different memory units, at least one spare read/write memory unit similar in operation to one of the read/write memory units of said plurality of read/write memory units and operating in parallel therewith, means for generating from the digits of a block of data and associated error correction code read from said memory units a digit which corrects a error in a digit read from one of said memory units, said generating means operating on a sequence of said blocks of data and associated error correction codes to generate a sequence of correct digits in place of a sequence of digits read from one of said memory units, and means for accessing the spare read/write memory unit to store therein said sequence of correct digits as the sequence of blocks of data and associated error correction codes are read from the plurality of read/write memory units.
Claim 15
Dependent Claim
58 words
The system of claim 11 further comprising first and second multiplexers, said first multiplexers selectively supplying to said plurality of read/write memory units either blocks of data and error correction codes or said sequence of correct digits of data and said second multiplexers supplying output signals from either said plurality of memory units or said spare memory unit.
Claim 16
Dependent Claim
69 words
The system of claim 12 wherein there are as many first multiplexers and as many second multiplexers as there are memory units in said plurality of read/write memory units, each said first multiplexer supplying one of said plurality of read/write memory units and each of said second multiplexers multiplexing signals from all of said spare memory units and a different one of each of said plurality of memory units.
Claim 17
Dependent Claim
21 words
The system of claim 11 wherein there are thirty-nine read/write memory units in said plurality of memory units and three spares.
Claim 18
Dependent Claim
21 words
The apparatus of claim 11 wherein each read/write memory unit and each spare read/write memory unit is an identical disk drive.
Claim 19
Independent Claim
251 words
The method of operating a multi-unit memory system comprising the steps of: generating for each block of data to be stored in said memory system an error correction code from which at least one bit of error may be detected and corrected in the block of data, each block of data comprising a first plurality of digits and each error correcting code comprising a second plurality of digits, storing in a plurality of read/write memory units blocks of data and associated error correction codes, data being written to said read/write memory units in parallel and data being read from said read/write memory units in parallel, each of the different digits of each code and its associated data block being stored at the same address in different memory units, generating from the digits of a block of data and associated error correction code read from said memory units a digit which corrects an error in a digit read from one of said memory units, said generating step operating on a sequence of said blocks of data and associated error correction codes to generate a sequence of correct digits in place of a sequence of digits read from one of said memory units, and storing in a spare read/write memory unit that operates in parallel to the read/write memory units of said plurality of read/write memory units said sequence of correct digits as the sequence of blocks of data and associated error correction codes are read from the plurality of read/write memory units.
Claim 20
Independent Claim
251 words
The method of operating a multi-unit memory system comprising the steps of: generating for each block of data to be stored in said memory system an error correction code from which at least one bit of error may be detected and corrected in the block of data, each block of data comprising a first plurality of digits and each error correcting code comprising a second plurality of digits, storing in a plurality of read/write memory units blocks of data and associated error correction codes, data being written to said read/write memory units in parallel and data being read from said read/write memory units in parallel, each of the different digits of each code and its associated data block being stored at the same address in different memory units, generating from the digits of a block of data and associated error correction code read from said memory units a digit which corrects an error in a digit read from one of said memory units, said generating step operating on a sequence of said blocks of data and associated error correction codes to generate a sequence of correct digits in place of a sequence of digits read from one of said memory units, and storing in a spare read/write memory unit that operates in parallel to the read/write memory units of said plurality of read/write memory units said sequence of correct digits as the sequence of blocks of data and associated error correction codes are read from the plurality of read/write memory units.
Claim 21
Dependent Claim
84 words
The method of claim 16 further comprising the steps of: repairing or replacing the memory unit from which said error was read, generating from a sequence of blocks of data and associated error correction codes read from said plurality of memory units except for the unit that was repaired or replaced a sequence of digits which recreate information previously stored in the memory unit which was repaired or replaced, and writing on the memory unit that was repaired or replaced said sequence of digits.
Claim 22
Dependent Claim
21 words
The method of claim 16 wherein each read/write memory unit and each spare read/write memory unit is an identical disk drive.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-02-05 | 1993-08-07 | 1994-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-05 | 1997-08-07 | 1998-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-05 | 2001-08-07 | 2002-02-06 | $7700.00 | Window Closed / Lapsed |