Cache memory for independent parallel accessing by a plurality of processors

Claim 2

A computer structure comprising: a plurality (m) of data buses including data bus lines; a cache memory including a plurality (k) of cache memory read ports for reading data therefrom, where k<m, and a plurality (p) of cache memory write ports for writing data thereinto, where p<m; each of said read ports and write ports including port lines extending to cross said data bus lines to form crosspoints therewith; a switching matrix network including said crosspoints and a plurality of controllable switches with at least one of said controllable switches at selected ones of said crosspoints; and a cache memory controller connected to and operable to selectively control said controllable switches for data transfer between said cache memory and said plurality of data buses, wherein each of said ports of said cache memory comprises a word width of i words and each of said buses comprises a width of j words where i>j and further wherein a maximum of i words can be switched in parallel to said cache memory from a plurality of processors.

Claim 3

A computer structure comprising: a plurality of data buses including data bus lines; a cache memory including a plurality of cache memory read ports for reading data therefrom and a plurality of cache memory write ports for writing data thereinto; each of said read and write ports including port lines extending to cross said data bus lines to form crosspoints therewith; a switching matrix network including said crosspoints and a plurality of controllable switches with at least one of said controllable switches at selected ones of said crosspoints; a cache memory controller connected to and operable to selectively control said controllable switches for data transfer between said cache memory and said plurality of data buses wherein said cache memory controller includes means for controlling said controllable switches to connect in parallel said data bus terminals to said cache memory; a plurality of processors; wherein each of said ports of said cache memory comprises a word width of i words; said buses comprise a width of j words; and a maximum of i words can be switched in parallel to said cache memory from said plurality of processors.

Claim 4

A computer structure comprising: a plurality of data buses including data bus lines; a cache memory including a plurality of cache memory read ports for reading data therefrom and a plurality of cache memory write ports for writing data thereinto; each of said read and write ports including port lines extending to cross said data bus lines to form crosspoints therewith; a switching matrix network including said crosspoints and a plurality of controllable switches with at least one of said controllable switches at selected ones of said crosspoints; a cache memory controller connected to and operable to selectively control said controllable switches for data transfer between said cache memory and said plurality of data buses wherein said cache memory controller includes means for controlling said controllable switches to connect in parallel said data bus terminals to said cache memory; a plurality of processors; wherein each of said ports of said cache memory comprises a word width of i words; said buses comprise a width of j words; and a maximum of i words can be switched in parallel to said cache memory from said plurality of processors.

Claim 5

The computer structure of claim 2, and further comprising: a main memory; and a memory bus connecting said main memory to said switching matrix network which forms additional crosspoints with said read and write ports; and additional controllable switches at selected ones of said additional crosspoints connected to and controlled by said cache memory controller.

Claim 6

The computer structure of claim 3, wherein: said cache memory comprises a plurality of separately drivable cache memory banks.

Claim 7

The computer structure of claim 2, wherein: said switching matrix network comprises said plurality of controllable switch elements arranged at intersections of rows and columns, said plurality of controllable switches being arranged at intersections of said switching matrix network for connecting lines of said data buses that are j words wide to lines of said ports that are i words wide.

Claim 8

The computer structure of claim 2, and further comprising: a multiplexer connected to provide, from a data bus, a word which is j words wide to port terminal lines that are i words wide.

Claim 9

The computer structure of claim 5, wherein: at least two of said controllable switches are provided per selected crosspoint; and further comprising: a plurality of word multiplexers connected to multiplex words from at least two of said port lines onto each of said memory ports that are i words wide, and each of said plurality of word multiplexers arranged between said cache memory ports and said port terminal lines of a respective column of said controllable switches of said switching matrix network.

Claim 10

The computer structure of claim 7, wherein: said plurality (p) of write ports is determined by the equation p≈round[[w.sub.w +w.sub.w-Miss *t.sub.w-La ]*n*w.sub.PBi /f](1) where p is the number of write ports, w w is the write access probability, w w-Miss is the probability of cache memory miss, t w -L a is the write access probability to the main memory, w PBi is the write access probability of the processor buses, n is the number of connected processors elements, and f is a factor corresponding to an average number of possible accesses, in parallel, per port.

Claim 11

The computer structure of claim 7, wherein: said plurality (k) of read ports is determined by the equation: k≈round[[w.sub.r +w.sub.r-Miss *t.sub.r-La ]*n*w.sub.PBi /f](2) where k is the number of read ports, w r is the read access probability, w r-Miss is the probability of a cache memory miss, t r-La is the read access time onto the main memory, w PBi is the mean access probability of the processor buses, n is the number of connected processor elements, and f is a factor corresponding to an average number of possible accesses, in parallel, per port.

Claim 12

The computer structure of claim 7, wherein, a separate read port is provided at the cache memory for the instruction unit.

Claim 13

The computer structure of claim 7, wherein: a separate write port for the cache memory is provided for the main memory.