Multi port time-shared associative buffer storage pool

Claim 2

A time-shared modular digital storage system for access and use by a plurality of independently functioning data ports supplying digital information comprising: a plurality of linearly interconnected memory cells for storing digital information, each memory cell having a name associated therewith when digital information is stored therein, each memory cell having associative addressing logic means for identifying the name associated with that particular memory cell; and control means cooperating with said data ports and said plurality of memory cells for accepting requests for access to memory cells from any of said data ports individually, each said request including a name and operational commands supplied by the requesting port, said control means further cooperating with the data ports and the memory cells for allocating access to a memory cell by a requesting data port when the supplied name matches the name associated with the memory cell; each said memory cell including name comparator means accepting supplied names from the control means for associatively detecting a match between a supplied name and the name associated with any of the memory cells, said name comparator means further including means assigning the supplied name to a memory cell in response to said operational requests when the supplied name fails to match the name associated with any of the memeory cells.

Claim 3

The time-shared digital storage system of claim 1 wherein each of said memory cells comprises: means for storing the digital information supplied by said data ports; said name comparator means including means for generating status signals in response to said match, said status signals indicating said matched memory cell is either available for access by the requesting data port or unavailable for access by the requesting data port; state control means receiving the operational commands from the data ports through the control means for attaching a memory cell to a requesting data port and for establishing a memory cell in either of three states in response to said operational commands, (1) an attached state wherein said memory cell is attached to a data port and has associated therewith a name matching the name supplied by the attached port, (2) an available state wherein said memory cell has a name associated therewith and is unattached to a data port or (3) a free state wherein said memory cell is not attached to a data port and does not have a name associated therewith and storage control means for controlling the transfer of digital information between the memory cell and an attached data port.

Claim 4

The time-shared digital storage system of claim 2 wherein said means for storing digital information is a shift register.

Claim 5

The digital storage system of claim 3 further including: a command buss associated with each of the data ports for transmitting the supplied name and operational commands to the control means; a control bus interconnecting the memory cells to the control means for transmitting supplied names and operational commands to said memory cells and for transmitting status signals from said memory cells to said control means; and a plurality of data busses singly associated with each of the ports for transferring digital information between the data ports and each of the memory cells at a transfer rate associated with the transferring data ports.

Claim 6

The digital storage system of claim 4 further including status lines interconnecting adjacent memory cells for transmitting to the succeeding memory cells a free signal from the state control means of the preceeding memory cell when said preceeding memory cell is in the free state.

Claim 7

A time-shared, modular, buffer memory storage pool comprising: a plurality of serially interconnected memory cells for storing digital information, each said memory cell having an identifying name associated therewith when digital information is stored therein a plurality of associative addressing logic means singly associated with respective memory cells for enabling simultaneous associative accessing of said memory cells in response to an access request; a plurality of independently functioning data ports attachable to said memory cells for transferring digital information to and from the memory cells at transfer rates associated with the data ports, said data ports supplying access requests to the memory cells, said access requests including the name associated with the memory cell to be accessed; and control means cooperating with the associative addressing logic means and with the data ports for accepting an access request for a memory cell from any of the data ports and for allocating access to the memory cell by the requesting data port if the name of the memory cell matches the supplied name and the memory cell is not attached to a data port; each said associated logic means including name comparator means accepting supplied names from the control means for associatively detecting a match between a supplied name and the name associated with any of the memory cells, said name comparator means further including means assigning the supplied name to a memory cell in response to said operational requests when the supplied name fails to match the name associated with any of the memory cells.

Claim 8

A time-shared, modular, buffer memory storage pool comprising: a plurality of serially interconnected memory cells for storing digital information, each said memory cell having an identifying name associated therewith when digital information is stored therein a plurality of associative addressing logic means singly associated with respective memory cells for enabling simultaneous associative accessing of said memory cells in response to an access request; a plurality of independently functioning data ports attachable to said memory cells for transferring digital information to and from the memory cells at transfer rates associated with the data ports, said data ports supplying access requests to the memory cells, said access requests including the name associated with the memory cell to be accessed; and control means cooperating with the associative addressing logic means and with the data ports for accepting an access request for a memory cell from any of the data ports and for allocating access to the memory cell by the requesting data port if the name of the memory cell matches the supplied name and the memory cell is not attached to a data port; each said associated logic means including name comparator means accepting supplied names from the control means for associatively detecting a match between a supplied name and the name associated with any of the memory cells, said name comparator means further including means assigning the supplied name to a memory cell in response to said operational requests when the supplied name fails to match the name associated with any of the memory cells.

Claim 9

The buffer memory storage pool of claim 6 wherein each of said memory cells include means for generating response signals in response to said access requests, said response signals indicating a match between a name supplied by a requesting data port and the name associated with a memory cell, said response signals further indicating whether said matched memory cell is available for access by said requesting data bus or whether said matched memory cell is attached to another of said data ports and unavailable for access by said requesting data port.

Claim 10

The buffer memory storage pool of claim 7 wherein each of said memory cells includes state control means for attaching a named memory cell to a requesting data port when the name supplied by the data port matches the name associated with a named memory cell.

Claim 11

The buffer memory storage pool of claim 7 further including: a plurality of command busses singly interconnecting respective data ports with the control means for transmitting access requests from said data ports to said control means; a control buss interconnecting the control means with the memory cells for transmitting access requests from the control means to the associative addressing logic means; a plurality of enable lines interconnecting each of said memory cells with their associated addressing logic means, said enable lines singly associated with respective data ports for enabling the transfer of digital information between a memory cell and a requesting data port when said requesting data port is attached to said memory cell; and a plurality of data busses singly interconnecting each of said data ports with each of said memory cells for the transfer of digital information therebetween.

Claim 12

The buffer memory system of claim 9 wherein said memory cell includes means for bidirectional serial transfer of information between said memory cell and an enabled and attached data port.

Claim 13

A time-shared digital data storage system for the transfer of data between independently functioning, requesting data ports responsive to access requests supplied by the data ports where said access requests include a storage operation, a name and data transfer clock signals, the storage system comprising: control means cooperating with the data port for accepting access requests therefrom; a plurality of linearly interconnected memory cells singly attachable to any of the data ports for accepting and storing data from an attached data port and transferring data to an attached data port in accordance with the storage operation and the data transfer clock signals supplied by the requesting data port, each said memory cell having a name associated therewith when data is stored therein associative addressing means associated with each memory cell for detecting a match between a name supplied by a requesting data port and a memory cell name for attaching said matched memory cell to said requesting data port, each of said associative addressing means further including means generating response signals indicating whether its associated memory cell is attached to a data port; each said associative logic means including means assigning the supplied name to a memory cell in response to said operational request when the supplied name fails to match the name associated with any of the memory cells; a control buss interconnecting the associative addressing means with the control means for transmitting storage operations and supplied names to the memory cells and for transmitting response signals from the memory cells to the control means; a plurality of enable busses singly provided to interconnect a memory cell with an associated associative addressing means; a data buss associated with each of the ports for transmitting data between the port and the memory cells; and full propogate means including status lines for generating status signals along said lines, said status lines interconnecting adjacent memory cells for transmitting to the succeeding cell a signal indicating the state of the preceeding cell.

Claim 14

A time-shared digital data storage system for the transfer of data between independently functioning, requesting data ports responsive to access requests supplied by the data ports where said access requests include a storage operation, a name and data transfer clock signals, the storage system comprising: control means cooperating with the data port for accepting access requests therefrom; a plurality of linearly interconnected memory cells singly attachable to any of the data ports for accepting and storing data from an attached data port and transferring data to an attached data port in accordance with the storage operation and the data transfer clock signals supplied by the requesting data port, each said memory cell having a name associated therewith when data is stored therein associative addressing means associated with each memory cell for detecting a match between a name supplied by a requesting data port and a memory cell name for attaching said matched memory cell to said requesting data port, each of said associative addressing means further including means generating response signals indicating whether its associated memory cell is attached to a data port; each said associative logic means including means assigning the supplied name to a memory cell in response to said operational request when the supplied name fails to match the name associated with any of the memory cells; a control buss interconnecting the associative addressing means with the control means for transmitting storage operations and supplied names to the memory cells and for transmitting response signals from the memory cells to the control means; a plurality of enable busses singly provided to interconnect a memory cell with an associated associative addressing means; a data buss associated with each of the ports for transmitting data between the port and the memory cells; and full propogate means including status lines for generating status signals along said lines, said status lines interconnecting adjacent memory cells for transmitting to the succeeding cell a signal indicating the state of the preceeding cell.

Claim 15

The digital data storage system of claim 10 wherein each of said memory cells includes means for storing digital data and for bidirectionally, serially transferring digital data between an attached data port and said memory cell.