Patent US4047381A successfully refreshed from Google Patents.
EP0284751A2
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Cache memory
Assignee: International Business Machines Corp
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Filing: 1988-02-12
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Granted: —
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Expires: 2008-02-12
Abstract
Abstract A cache memory (50) consists of M partitions of independently addressed set associative memory in a single memory complex having N ports of access to the M partitions where N is less than or equal to M. Control means (54, 56) direct input addresses in a global fashion to all partitions or in a local fashion to a particular set of partitions specified as the output of PLATs (100, 102, ..., 108) which receive memory request addresses. The PLAT either hits and provides the desired partition identifier or misses and a global request of the cache memory (50) must occur. If a global request of all partitions of a cache memory (50) occurs and creates a hit, a new PLAT entry is created to identify the partition in which the desired information is stored.
Inventors
- 👤 James Gerald Brenza
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 03:26
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0864; G06F12/0806; G06F12/084
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
174 words
Cache memory, characterized by M partitions of independently addressed set associative memory in a single memory (50) complex; by address bus switching means (58) for providing N ports of address access to said M partitions where N is less than or equal to M; by data bus switching means (52) for providing N ports of data access to said M partitions; by control means (54, 56) for controlling said address bus switching means (58) for switching addresses to selected partitions of said set associative memory and for controlling said data bus switching means (52) for switching inputs and outputs of said partitions to selected data busses; and by PLAT means (100, 102, ..., 108) for receiving memory requests and controlling said address bus and said data bus switching means to direct a memory request to a selected single partition as a result of information contained in said PLAT means in the case of a read operation and to direct a memory request to a single selected partition in the case of a store operation.
Claim 2
Dependent Claim
174 words
Cache memory, characterized by M partitions of independently addressed set associative memory in a single memory (50) complex; by address bus switching means (58) for providing N ports of address access to said M partitions where N is less than or equal to M; by data bus switching means (52) for providing N ports of data access to said M partitions; by control means (54, 56) for controlling said address bus switching means (58) for switching addresses to selected partitions of said set associative memory and for controlling said data bus switching means (52) for switching inputs and outputs of said partitions to selected data busses; and by PLAT means (100, 102, ..., 108) for receiving memory requests and controlling said address bus and said data bus switching means to direct a memory request to a selected single partition as a result of information contained in said PLAT means in the case of a read operation and to direct a memory request to a single selected partition in the case of a store operation.
Claim 3
Dependent Claim
36 words
Cache memory of Claim 1, characterized in that in the PLAT means a global memory request is issued to all M partitions of said cache when a particular partition cannot be identified for a memory operation.
Claim 4
Dependent Claim
37 words
Cache memory of Claim 1, characterized in that in the PLAT means a plurality of PLATs are each associated with a memory using element so that each memory using element may direct requests to its own PLAT.
Claim 5
Dependent Claim
36 words
Cache memory of Claim 1 including at least two PLATs, one of which is designed to operate in the memory read mode and the other of which is designed to operate in the memory write mode.
Claim 6
Dependent Claim
31 words
Cache memory of Claim 1 including at least two PLATs, one of which is an instruction entry handling PLAT type and the other of which is a data handling PLAT type.
Claim 7
Dependent Claim
70 words
Cache memory of Claim 1, characterized in that each PLAT means (100, 102, ..., 108) contains entries associating addresses with partition location identifiers and in which each entry further includes a valid bit (V) and a valid/store bit (V/S), wherein the valid bit indicates if the partition entry for an address is valid or should be ignored and the valid/store bit indicates that a store interrogate operation has been made.
Claim 8
Dependent Claim
103 words
Cache memory of Claim 1, characterized by fault test logic means (40) for determining if one of said partitions has failed; invalid partition indicating register (702) having a position for each of M partitions and for receiving and storing an indication from said fault test logic means (40) that a partition has failed; and means (708, 712, 720, 722) for assigning new storage requests to selected partitions of said cache connected to said invalid partition indicating register (702) whereby said means for assigning is responsive to said invalid partition indicating register so that new storage requests are not assigned to a failed partition.
Claim 9
Dependent Claim
39 words
Cache memory of Claim 7, characterized in that means for assigning new storage requests is a least recently used logic unit (712) which sets the next partition to be used in advance at the time of a storage request.
Claim 10
Dependent Claim
113 words
Cache memory of Claim 1, characterized in that the PLAT means includes means for storing a valid bit, a valid store bit and a partition identifier for each address in the PLAT whereby both the valid bit and the valid store bit must be present in addition to the address in order to get a PLAT hit for store requests and further including a cache directory for said cache, means for setting said valid store bit when a PLAT entry is created for both a store or fetch operation in response to a PLAT miss and means for making a store interrogate operation of said cache directory in response to a PLAT miss.
Claim 11
Dependent Claim
56 words
Cache memory of Claim 9, characterized by logic means for setting said valid store bit and for reading said valid store bit so that if said bit is off, a PLAT miss will occur for a store request to the associated address and a PLAT hit will occur for a read request to the associated address.
Claim 12
Dependent Claim
115 words
Cache memory of Claim 1, characterized by local control out means connected from each of said M cache partitions to said PLAT where each of said M partitions makes a request identifiable to it, said means identifying to said PLAT the partition identifier for a new PLAT entry; local control in means connected from said PLAT means to each of said M cache partitions for making an access request specific to a particular partition; global request control means for making an access request of all of said M partitions simultaneously, and wherein; control means in said PLAT means for activating said global request control means in response to a PLAT miss to an access request.
Claim 13
Dependent Claim
131 words
Cache memory of Claim 1, characterized by line fetch buffer means (110) for storing new lines into cache on request wherein said line fetch buffer means requires access to a single selected cache partition when storing the contents of said line fetch buffer means into cache and all other cache partitions operate normally; and by means for identifying selected partitions with memory requests in a table and for receiving memory requests and controlling said address bus and said data bus switching means to direct a memory request to a selected single partition as a result of in formation contained in said means for identifying selected partitions in the case of a read operation and to direct a memory request to a single selected partition in the case of a store operation.
Claim 14
Dependent Claim
97 words
Cache memory of Claim 12 wherein said means for identifying selected partitions is comprised of a plurality of PLAT means wherein each PLAT means is characterized by at least one set of set associative registers (300) for holding cache address identifiers arranged in at least M congruency classes; means for receiving an input address request (322); comparator means (328) for comparing the contents of said set of set associative registers with said means for receiving an input address request and providing a partition identifier if a hit occurs and a miss indication if no compare is made.
Claim 15
Dependent Claim
68 words
Cache memory of Claim 13 wherein at least one of said PLAT means is characterized by means for storing and associating a valid store bit with each address and partition identifier and logic means for causing a PLAT miss for a write request to an address for which the bit is not set and for allowing a read request when the bit is either set or not set.
Claim 16
Dependent Claim
33 words
The PLAT means of Claim 13 in which a global memory request is issued to all M partitions of said cache when a particular partition cannot be identified for a memory read operation.
Claim 17
Dependent Claim
33 words
The PLAT means of Claim 13 in which a plurality of PLATs are each associated with a memory using element so that each memory using element may direct requests to its own PLAT.
Claim 18
Dependent Claim
37 words
The PLAT means of Claim 13 including at least two PLATs, one of which is designed to operate in the memory read mode and the other of which is designed to operate in the memory write mode.
Claim 19
Dependent Claim
32 words
The PLAT means of Claim 13 including at least two PLATs, one of which is an instruction entry handling PLAT type and the other of which is a data handling PLAT type.
Claim 20
Dependent Claim
39 words
Cache memory of any of Claims 1 - 18, characterized in that a plurality of selected cache operations may occur on each cache cycle with one operation occurring at each partition associated with a port for that cache cycle.
Claim 21
Dependent Claim
69 words
Cache memory of any of Claims 1 - 19, characterized in that each PLAT contains entries associating addresses with partition location identifiers and in which each entry further includes a valid bit (V) and a valid/store bit (V/S), wherein the valid bit indicates if the partition entry for an address is valid or should be ignored and the valid/store bit indicates that a store interrogate operation has been made.
References Cited (Backward Citations)
No citation records indexed.
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