Methods for fabricating and operating electrically erasable and programmable integrated circuit memory

Claim 1

A method for fabricating an integrated circuit memory cell, comprising the steps of: (a) providing a body of monocrystalline semiconductor material; (b) forming a patterned field insulation layer which exposes said semiconductor material in a location to provide an active area of a first conductivity type; (c) forming a gate insulation layer over said active area and a first thin film conductor layer over said gate insulation layer; and patterning said first conductor layer to provide, in each memory cell location, a laterally isolated floating gate which crosses said active area to define a channel region; (d) implanting said active area, where not covered by said first conductive layer, with dopants of a second conductivity type, to form source extension and drain extension diffusions in said active region on opposite sides of said channel region; (e) implanting second conductivity type dopants, at higher dose and energy than said implanting step (d), to form a source diffusion which is continuous with said source extension, and a drain diffusion which is continuous with said drain extension; (f) forming an interlevel insulation layer over said first conductor and a second thin film conductor layer over said interlevel insulation layer, and patterning said second conductor layer to provide, in each location of a memory cell: a portion of said second conductor layer which overlies and is capacitively coupled to said floating gate, and which is laterally extended to define a control gate; and another portion of said second conductor layer which overlies and is capacitively coupled to said floating gate, and which is electrically connected to said drain to define a drain coupling element, and is otherwise isolated.

Claim 2

A method for fabricating an integrated circuit memory cell, comprising the steps of: (a) providing a body of monocrystalline semiconductor material; (b) forming a patterned field insulation layer which exposes said semiconductor material in a location to provide an active area of a first conductivity type; (c) forming a gate insulation layer over said active area and a first thin film conductor layer over said gate insulation layer; and patterning said first conductor layer to provide, in each memory cell location, a laterally isolated floating gate which crosses said active area to define a channel region; (d) implanting said active area, where not covered by said first conductive layer, with dopants of a second conductivity type, to form source extension and drain extension diffusions in said active region on opposite sides of said channel region; (e) implanting second conductivity type dopants, at higher dose and energy than said implanting step (d), to form a source diffusion which is continuous with said source extension, and a drain diffusion which is continuous with said drain extension; (f) forming an interlevel insulation layer over said first conductor and a second thin film conductor layer over said interlevel insulation layer, and patterning said second conductor layer to provide, in each location of a memory cell: a portion of said second conductor layer which overlies and is capacitively coupled to said floating gate, and which is laterally extended to define a control gate; and another portion of said second conductor layer which overlies and is capacitively coupled to said floating gate, and which is electrically connected to said drain to define a drain coupling element, and is otherwise isolated.