US5058069A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for addressing of redundant elements of an integrated circuit memory
Assignee: Thomson Semiconducteurs SA
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Filing: 1990-01-17
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Granted: 1991-10-15
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Expires: 2010-01-17
Abstract
Abstract A device for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, and at least one group of fuses to store the address of a faulty element of the memory. Each fuse is associated with a row/column address pair. Through the blowing of certain fuses in the group after testing of a memory element, the address either of a column element, if the faulty element is a column element, or of a row element, if the faulty element is a row element, is stored. Only the row addresses are enabled when the stored address is that of a row element, and only the column addresses are enabled when the stored address is that of a column element, in order to address either a row redundant element or a column redundant element.
Inventors
- 👤 Jean Marie Gaultier
- 👤 Jean Devin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:03
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/80; G11C29/808
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
192 words
An integrated circuit memory comprising an array of memory cells addressable by means of a row address and each column of memory cells addressable by means of a column address, said memory further comprising at least one redundant group of cells comprising a redundant row of cells and a redundant column of cells, with means for connecting said redundant row in replacement of a defective row of the array and means for connecting said redundant column in replacement of a defective column of the array, said memory further comprising for each group of a redundant row and column one storing means capable of storing either an address of a defective row or an address of a defective column but not both, said memory further comprising enabling means for either enabling memorization in said storing means of the address of a given row and enabling selection of a first connecting path allowing replacement of said given row by said redundant line, or enabling memorization in said storing means of the address of a given column and enabling selection of a second connecting path allowing replacement of said given column by said redundant column.
Claim 2
Dependent Claim
192 words
An integrated circuit memory comprising an array of memory cells addressable by means of a row address and each column of memory cells addressable by means of a column address, said memory further comprising at least one redundant group of cells comprising a redundant row of cells and a redundant column of cells, with means for connecting said redundant row in replacement of a defective row of the array and means for connecting said redundant column in replacement of a defective column of the array, said memory further comprising for each group of a redundant row and column one storing means capable of storing either an address of a defective row or an address of a defective column but not both, said memory further comprising enabling means for either enabling memorization in said storing means of the address of a given row and enabling selection of a first connecting path allowing replacement of said given row by said redundant line, or enabling memorization in said storing means of the address of a given column and enabling selection of a second connecting path allowing replacement of said given column by said redundant column.
Claim 3
Dependent Claim
28 words
An integrated circuit memory according to claim 1, wherein said enabling means comprises a fusable link, the state of the fuse defining which memorization and selection is enabled.
Claim 4
Dependent Claim
59 words
An integrated circuit according to claim 1 wherein a memory cell is addressable by means of N bits of addresss of row and P bits of address of column, and said storing means comprises a group of fusable links, the number of fusable links of said storing means being equal to whichever is the greater of N and P.
Claim 5
Dependent Claim
30 words
An integrated memory circuit according to claim 3, wherein said enabling means comprises a further fusable link, the state of said fusable link defining which memorization and selection is enabled.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |