EP0443515A2
Expired / Lapsed
EP
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Nonvolatile semiconductor device
Assignee: Toshiba Corp
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Filing: 1991-02-19
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Granted: —
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Expires: 2011-02-19
Abstract
Abstract A nonvolatile semiconductor device according to the present invention comprises a memory cell array (14) having memory cells arranged in matrix, each memory cell being composed of floating gate electrode (5a, 5b, 5c, 5d), control gate electrode (9a, 9b), a source diffusion layer (2), and drain diffusion layer (3a, 3b, 3c, 3d), tunnel oxide films (6a, 6b, 6c, 6d) formed on the side walls of the floating gate electrodes on the side where adjacent memory cells, sharing the control gate electrode, face each other, and an erasure gate electrode (7) formed so as to sandwich the tunnel oxide films between the floating gate electrodes and itself, and electrically connected to the source diffusion layer at nearly an equal distance from the adjacent memory cells sharing the control gate electrode.
Inventors
- 👤 Kuniyoshi C/O Intellectual Prop. Div. Yoshikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 00:29
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10D30/684; H10D30/685; H10D30/6891; H10D30/6892
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
125 words
A nonvolatile semiconductor device, characterized by comprising: a memory cell array (14) having memory cells arranged in matrix, each memory cell being composed of floating gate electrode (5a, 5b, 5c, 5d), control gate electrode (9a, 9b), a source diffusion layer (2) and drain diffusion layer (3a, 3b, 3c, 3d); tunnel oxide films (6a, 6b, 6c, 6d) each formed on the side walls of said floating gate electrode on the side where adjacent cells, sharing said control gate electrode, face each other; and an erasure gate electrode (7) formed so as to sandwich said tunnel oxide films between said floating gate electrodes and itself, and electrically connected to said source diffusion layer at an nearly equal distance from the adjacent memory sharing said control gate electrode.
Claim 2
Dependent Claim
28 words
The nonvolatile semiconductor device according to claim 1, characterized in that said source diffusion layer (2) is shared by memory cells having said control gate electrode in common.
Claim 3
Dependent Claim
69 words
The nonvolatile semiconductor device according to claim 1, characterized in that said source diffusion layer (2) or drain diffusion layer is composed of a stack of a first and second impurity regions of different concentrations, the concentration of the first impurity region (2a) tuch a channel region just below said floating gate electrode being lower than that of the second impurity region (2b) just below said erasure gate electrode.
Claim 4
Dependent Claim
47 words
The nonvolatile semiconductor device according to claim 1, characterized in that said tunnel oxide film (6a, 6b, 6c, 6d) is formed in a region containing the side wall of said floating gate electrode on the side where memory cells sharing said control gate electrode face each other.
Claim 5
Dependent Claim
38 words
The nonvolatile semiconductor device according to claim 1, characterized in that charges in said floating gate move through said tunnel oxide film to said erasure gate electrode when a specific potential is applied to said erasure gate electrode.
Claim 6
Dependent Claim
29 words
The nonvolatile semiconductor device according to claim 1, characterized in that said erasure gate electrode (7) is shared by adjacent memory cells having said control gate electrode in common.
Claim 7
Dependent Claim
49 words
The nonvolatile semiconductor device according to claim 1, characterized in that said erasure gate electrode (7) is shared by adjacent memory cells in a row which have said control gate electrode in common, and by adjacent memory cells in a column which have said source diffusion layer in common.
Claim 8
Dependent Claim
36 words
The nonvolatile semiconductor device according to claim 1, characterized in that said floating gate electrode (5a, 5b, 5c, 5d) is made from polysilicon or silicide, or made up of a stacked structure of polysilicon and silicide.
Claim 9
Dependent Claim
34 words
The nonvolatile semiconductor device according to claim 1, characterized in that said control gate electrode (9a, 9b) is made from polysilicon or silicide, or made up of a stacked structure of polysilicon and silicide.
Claim 10
Dependent Claim
20 words
The nonvolatile semiconductor device according to claim 1, characterized in that said erasure gate electrode (7) is made from polysilicon.
Claim 11
Dependent Claim
24 words
The nonvolatile semiconductor device according to claim 1, characterized in that said tunnel oxide film (6a, 6b, 6c, 6d) is made from polysilicon film.
Claim 12
Dependent Claim
109 words
The nonvolatile semiconductor device according to claim 1, characterized in that each of said memory cells is composed of: a semiconductor substrate (1); a source diffusion layer (2a, 2b) and drain diffusion layer (3a, 3b, 3c, 3d) formed in the surface region of said semiconductor substrate; channel region between said source diffusion layer and drain diffusion layer; first insulating film (4a, 4b) formed above said channel region; floating gate electrode (5a, 5b, 5c, 5d) formed on said first insulating film and put in an electrically floating state; second insulating film (8a, 8b) formed on said floating gate electrode; and control gate electrode (9a, 9b) formed on said insulating film.
Claim 13
Dependent Claim
126 words
The nonvolatile semiconductor device according to claim 1, characterized in that each of said memory cells is composed of: a semiconductor substrate (1); a source diffusion layer (2a, 2b) and drain diffusion layer (3a, 3b, 3c, 3d) formed in the surface region of said semiconductor substrate; channel region between said source diffusion layer and drain diffusion layer; first insulating film (4a, 4b) formed above said channel region; floating gate electrode (5a, 5b, 5c, 5d) formed above said channel region close to said drain diffusion layer and put in an electrically floating state; second insulating film (8a, 8b) formed on said floating gate electrode; and control gate electrode (9a, 9b) formed on said second insulating film and above said channel region close to said source diffusion layer.
Claim 14
Dependent Claim
125 words
A nonvolatile semiconductor device, characterized by comprising: a memory cell array (14) having memory cells arranged in matrix, each memory cell being composed of floating gate electrode (5a, 5b, 5c, 5d), control gate electrode (9a, 9b), a source diffusion layer (2), and drain diffusion layer (3a, 3b, 3c, 3d); tunnel oxide films (6a, 6b, 6c, 6d) each formed on the side walls of said floating gate electrode on the side where adjacent cells, sharing said control gate electrode, face each other; and an erasure gate electrode (7) formed so as to sandwich said tunnel oxide films between said floating gate electrodes and itself, and electrically connected to said drain diffusion layer at an nearly equal distance from the adjacent memory sharing said drain diffusion layer.
References Cited (Backward Citations)
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