US5099451A
Expired / Lapsed
US
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Memory array with electrically programmable memory cells and electricaly unprogrammable, unerasable memory cells, both types of memory cells having floating gate transistors
Assignee: STMicroelectronics SA
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Filing: 1988-11-16
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Granted: 1992-03-24
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Expires: 2008-11-16
Abstract
Abstract To avoid differentiation, in manufacture, between the random-access memory cells and read-only memory cells of the same memory array, the memory cells are all made by the same technology. These memory cells employ essentially floating gate transistors. The random-access memory cells are programmed, in a stand way, by injecting or not electronic charges in the floating gates of the transistors. The read-only memory cells are put in a programmed or an unprogrammed state by the selective implantation of impurities or not in the conduction channels of the floating gate transistors of these memory cells. There is an improved concealment of the content, which is designed to remain concealed, of these memory cells, at the same time, the conditions for making prototypes to order are improved.
Inventors
- 👤 Laurent Sourgen
- 👤 Gilles Lisimaque
- 👤 Jean Devin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:50
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; G; G11; G11C; G11C11/00; G11C11/005; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/0433; G11C16/06; G11C16/10; H10B20/36; H10B20/363; H10B20/367; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
141 words
A memory array of cells comprising floating gate transistor electrically programmable memory cells, and floating gate transistor read-only memory cells which cannot be written or erased; each floating gate transistor having a channel; the channel of the floating gate transistor of each read-only memory cell being selectively doped with impurities or not doped with impurities depending on whether a programmed state or an unprogrammed state is desired; means for reading the electrically programmable memory cells and the read-only memory cells with each cell being read producing a voltage corresponding to information stored therein, said means for reading comprising means for comparing the voltage of the cell being read with a first reference voltage if the cell being read is an electrically programmable cell, or with a second and different reference voltage if the cell being read is a read-only memory cell.
Claim 2
Dependent Claim
141 words
A memory array of cells comprising floating gate transistor electrically programmable memory cells, and floating gate transistor read-only memory cells which cannot be written or erased; each floating gate transistor having a channel; the channel of the floating gate transistor of each read-only memory cell being selectively doped with impurities or not doped with impurities depending on whether a programmed state or an unprogrammed state is desired; means for reading the electrically programmable memory cells and the read-only memory cells with each cell being read producing a voltage corresponding to information stored therein, said means for reading comprising means for comparing the voltage of the cell being read with a first reference voltage if the cell being read is an electrically programmable cell, or with a second and different reference voltage if the cell being read is a read-only memory cell.
Claim 3
Dependent Claim
30 words
A memory array according to claim 1 wherein the memory array further comprises at least one bit line connected to both read only memory cells and electrically programmable memory cells.
Claim 4
Dependent Claim
39 words
A memory array according to claim 1 or 2 wherein the memory array further comprises at least one bit line connected only to read-only memory cells and at least another bit line connected to only electrically programmable memory cells.
References Cited (Backward Citations)
JPS56165984A
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US4618943A
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EP0224206A2
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EP0227965A2
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US4758984A
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EP0239283A2
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-24 | 1995-09-23 | 1996-03-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-24 | 1999-09-23 | 2000-03-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-24 | 2003-09-23 | 2004-03-24 | $7700.00 | Window Closed / Lapsed |