EP0183235A2
Expired / Lapsed
EP
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Nonvolatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1985-11-26
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Granted: —
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Expires: 2005-11-26
Abstract
Abstract A nonvolatile semiconductor memory device has n + - type source and drain regions (SR, DR) formed in the surface of a p-type semiconductor substrate, a floating gate (FG) formed above and insulated from a channel region (CR) provided between the source and drain regions (SR, DR), and a control gate (CG) formed above and insulated from the floating gate (FG). The memory device further has a capacitor (16) provided between the control gate (CG) and drain region (DR).
Inventors
- 👤 Naohiro Patent Division Matsukawa
- 👤 Yoshihisa Patent Division Mizutani
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 18:33
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
91 words
A nonvolatile semiconductor memory device comprising: a floating gate MOS transistor (10; 54) in which a control voltage is applied between the control gate (CG) and one end of the current path (SR, DR) and which stores data corresponding to the control voltage; characterized by further comprising capacitive means (16; 56), connected between said control gate (CG) and said one end of the current path (SR, DR) to be charged by the control voltage and to continuously apply the control voltage to said floating gate MOS transistor (10) after being charged.
Claim 2
Dependent Claim
91 words
A nonvolatile semiconductor memory device comprising: a floating gate MOS transistor (10; 54) in which a control voltage is applied between the control gate (CG) and one end of the current path (SR, DR) and which stores data corresponding to the control voltage; characterized by further comprising capacitive means (16; 56), connected between said control gate (CG) and said one end of the current path (SR, DR) to be charged by the control voltage and to continuously apply the control voltage to said floating gate MOS transistor (10) after being charged.
Claim 3
Dependent Claim
35 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said capacitive means (16) is connected between said control gate (CG) and the drain region (DR) of the floating gate MOS 'transistor (10).
Claim 4
Dependent Claim
82 words
A nonvolatile semiconductor memory device according to claim 2, characterized in that the source and drain regions (SR, DR) of said floating gate MOS transistor (10) are formed in the surface of a semiconductor substrate (12; 30; 50) and the floating gate (FG) of said floating gate MOS transistor (10) is formed over and insulated from said drain region (DR) and formed over and insulated from the channel region (CR) of said substrate provided between said source and drain regions (SR, DR).
Claim 5
Dependent Claim
33 words
A nonvolatile semiconductor memory device according to claim 3, characterized in that the control gate (CG) of said floating gate MOS transistor (10) is formed over and insulated from said floating gate (FG).
Claim 6
Dependent Claim
37 words
A nonvolatile semiconductor memory device according to claim 4, characterized in that said capacitive means (16) includes a conductive layer (36; formed over and insulated from said control gate (CG) in contact with said drain region (DR).
Claim 7
Dependent Claim
40 words
A nonvolatile semiconductor memory device according to claim 3, characterized in that the control gate (CG) of said floating gate MOS transistor (19) is formed in the surface of said semiconductor substrate (30) and insulated from said floating gate (FG).
Claim 8
Dependent Claim
35 words
A nonvolatile semiconductor memory device according to claim 6, characterized in that said capacitive means (16) includes a conductive layer (32) formed over and insulated from said control gate (CG) and said drain region (DR).
Claim 9
Dependent Claim
38 words
A nonvolatile semiconductor memory device according to claim 2, characterized by further comprising transfer means (20, 22, BL1, BL2, WL) for transferring the control voltage to said floating gate MOS transistor (10) in response to a select signal.
Claim 10
Dependent Claim
85 words
A nonvolatile semiconductor_memory device according to claim 8, characterized in that said transfer means includes a word line (WL) for receiving the select signal, first and second bit lines (BL1, BL2) for receiving the control voltage and first and second switching means (20, 22) which are connected between said first bit line (BL1) and said control gate (CG) and between said second bit line (BL2) and said drain region (DR) and are turned on responsive to the select signal supplied from the word line (WL).
Claim 11
Dependent Claim
104 words
A nonvolatile semiconductor memory device according to claim 9, characterized in that the source region and drain regions (SR, DR) and control gate (CG) of said floating gate MOS transistor (10) are formed in the surface of a semiconductor substrate (30), the floating gate (FG) of said floating gate MOS transistor (10) is formed over and insulated from said drain region ( D R), said control gate (CG) and the channel region (CR) between said source and drain regions (SR, DR), and said capacitive means (16) includes a conductive layer (32) formed over and insulated from said control gate (CG) and drain region (DR).
Claim 12
Dependent Claim
51 words
A nonvolatile semiconductor memory device according to claim 10, characterized in that said first switching means is an insulation gate MOS transistor (20) whose current path contacts said control gate (CG), and said second switching means is an insulation gate MOS transistor (22) whose current path contacts said drain region (DR).
Claim 13
Dependent Claim
117 words
A nonvolatile semiconductor memory device according to claim 9, characterized in that the source and drain regions (SR, DR) of said floating gate MOS transistor (10) are formed in the surface of said semiconductor substrate (30), the floating gate (FG) of said floating gate MOS transistor (10) is formed over and insulated from the channel region (CR) of said substrate (12) provided between said source and drain regions (SR, DR) and formed over and insulated from said drain region (DR), and control gate (CG) formed over and insulated from said floating gate (FG), and said capacitive means (16) includes a conductive layer formed over and insulated from said control gate (CG) and contacting said drain region (DR).
Claim 14
Dependent Claim
35 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said capacitive means (56) is connected between said control gate (CG) and the source region (SR) of the floating gate MOS transistor (54).
Claim 15
Dependent Claim
90 words
A nonvolatile semiconductor memory device according to claim 13, characterized in that the source and drain regions (SR, DR) of said floating gate M O S transistor (54) are formed in the surface of a semiconductor substrate (50), the floating gate (FG) of said floating gate MOS transistor (10) is formed over and insulated from the channel region (CR) provided between said source and drain regions (SR, DR), and the control gate (CG) of said floating gate MOS transistor (lU) is formed over and insulated from said floating gate (F6).
Claim 16
Dependent Claim
36 words
A nonvolatile semiconductor memory device according to claim 13, characterized by further comprising transfer means (58, WL, BL) for transferring the control voltage to said floating gate MOS transistor (54) in response to a select signal.
Claim 17
Dependent Claim
66 words
A nonvolatile semiconductor memory device according to claim 15, characterized in that said transferring means includes a bit line (BL) for receiving the control voltage, a word line (WL) for receiving the select signal, and switching means (58) which is connected between said bit line (BL) and said control gate (CG) and is turned on responsive to said select signal supplied from the word line (WL).
Claim 18
Independent Claim
66 words
A method of operating a nonvolatile semiconductor memory device according to any one of claims 1 to 16 in which method said control voltage is applied between said control gate (CG) and said one end of the current path (SR,DR) and in which said capacitive means (16;56) is charged by said control voltage and continu- ousl y thereafter applies said voltage to the MOS transistor (10).
References Cited (Backward Citations)
No citation records indexed.
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