Patent US5619063A successfully refreshed from Google Patents.
US5619063A
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Edgeless, self-aligned, differential oxidation enhanced and difusion-controlled minimum-geometry antifuse and method of fabrication
Assignee: Microsemi SoC Corp
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Filing: 1995-12-12
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Granted: 1997-04-08
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Expires: 2015-12-12
Abstract
Abstract The present invention is directed to an antifuse structure and fabrication process wherein the bottom oxide of the ONO antifuse material layer is grown over a small area of N- diffusion surrounded by an N+ diffusion area where the N- diffusion could be patterned as N- "islands" or as N- "stripes", or the like, with the active N- area controlled by the formation and drive-in of the N+ diffusion layer. In this way, the bottom oxide layer of the ONO antifuse material layer is thinner at its center (above the N- region) than at its edges because oxide grows slower on the less doped N- region at the center of the antifuse than at the more heavily doped N+ regions at the edges of the antifuse. Forcing the center of the antifuse material layer to be thinner causes the antifuse to preferentially break down at its center and away from its edges. The opening in the antifuse cell opening mask is wider than the width of the N- diffusion area so that both N- and N+ areas are exposed in the antifuse cell opening step. Since the N+ diffusion can be very accurately dimensionally controlled with known techniques, it is thus possible to reduce the dimension of the active N- diffusion down to 0.2 μm or below, comparing favorably with the linear dimension of 1.0 μm used in currently available state-of-the-art manufacturing processes for antifuses. This represents a factor of 25 reduction in the active antifuse area, which in turn can dramatically reduce the defect density of antifuses over current technology and/or dramatically increase the number of antifuses that may be disposed in a given area of silicon.
Inventors
- 👤 Wenn-Jei Chen
- 👤 Huang-Chung Tseng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:22
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/491
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
168 words
An antifuse comprising: a lower antifuse electrode including an N- diffusion region disposed within, surround by and in contact with an N+ diffusion region disposed generally about a vertical axis of said N- diffusion region; an isolation layer means; an antifuse cell opening of a first area in and through said isolation layer means; an upper electrode means; an antifuse material layer disposed between said lower antifuse electrode and said upper electrode means and over and in contact with said lower antifuse electrode; and means for rupturing said antifuse within a predetermined second area much smaller than said first area, said second area being at a predetermined location confined within said antifuse cell opening, said means including causing said antifuse material layer deposited over said lower antifuse electrode to be of a first minimum thickness in a region over said N+ diffusion region and of a second minimum thickness in a region over said N- diffusion region, said first minimum thickness being greater than said second minimum thickness.
Claim 2
Dependent Claim
168 words
An antifuse comprising: a lower antifuse electrode including an N- diffusion region disposed within, surround by and in contact with an N+ diffusion region disposed generally about a vertical axis of said N- diffusion region; an isolation layer means; an antifuse cell opening of a first area in and through said isolation layer means; an upper electrode means; an antifuse material layer disposed between said lower antifuse electrode and said upper electrode means and over and in contact with said lower antifuse electrode; and means for rupturing said antifuse within a predetermined second area much smaller than said first area, said second area being at a predetermined location confined within said antifuse cell opening, said means including causing said antifuse material layer deposited over said lower antifuse electrode to be of a first minimum thickness in a region over said N+ diffusion region and of a second minimum thickness in a region over said N- diffusion region, said first minimum thickness being greater than said second minimum thickness.
Claim 3
Dependent Claim
168 words
Anantifuse comprising: a lower antifuse electrode including an N- diffusion region in the shape of a trench disposed within, surrounded on either side of said trench by and in contact with an N+ diffusion region; an isolation layer means; an antifuse cell opening of a first area in and through said isolation layer means; an upper electrode means; an antifuse material layer disposed between said lower antifuse electrode and said upper electrode means and over and in contact with said lower antifuse electrode; and means for rupturing said antifuse within a predetermined second area much smaller than said first area, said second area being at a predetermined location confined within said antifuse cell opening, said means including causing said antifuse material layer deposited over said lower antifuse electrode to be of a first minimum thickness in a region over said N+ diffusion region and of a second minimum thickness in a region over said N- diffusion region, said first minimum thickness being greater than said second minimum thickness.
Claim 4
Dependent Claim
168 words
Anantifuse comprising: a lower antifuse electrode including an N- diffusion region in the shape of a trench disposed within, surrounded on either side of said trench by and in contact with an N+ diffusion region; an isolation layer means; an antifuse cell opening of a first area in and through said isolation layer means; an upper electrode means; an antifuse material layer disposed between said lower antifuse electrode and said upper electrode means and over and in contact with said lower antifuse electrode; and means for rupturing said antifuse within a predetermined second area much smaller than said first area, said second area being at a predetermined location confined within said antifuse cell opening, said means including causing said antifuse material layer deposited over said lower antifuse electrode to be of a first minimum thickness in a region over said N+ diffusion region and of a second minimum thickness in a region over said N- diffusion region, said first minimum thickness being greater than said second minimum thickness.
Claim 5
Dependent Claim
153 words
An antifuse disposed over a silicon substrate comprising: a lower antifuse electrode including an N- diffusion region disposed adjacent to and in contact with an N+ diffusion region, said N+ diffusion region surrounging said N- diffusion region; an isolation oxide layer disposed over said lower antifuse electrode; an antifuse cell opening of a first area in and through said isolation oxide layer; an antifuse material layer disposed in said antifuse cell opening and over and in physical contact with said N- diffusion region, said antifuse material layer including a first oxide layer of non-uniform thickness having its thinnest portion directly over said N- diffusion region; and an upper antifuse electrode disposed over said antifuse material layer; wherein said antifuse is adapted to rupture within a second area much smaller than said first area, said second area being at a predetermined location within said antifuse cell opening and located above said N- diffusion region.
Claim 6
Dependent Claim
153 words
An antifuse disposed over a silicon substrate comprising: a lower antifuse electrode including an N- diffusion region disposed adjacent to and in contact with an N+ diffusion region, said N+ diffusion region surrounging said N- diffusion region; an isolation oxide layer disposed over said lower antifuse electrode; an antifuse cell opening of a first area in and through said isolation oxide layer; an antifuse material layer disposed in said antifuse cell opening and over and in physical contact with said N- diffusion region, said antifuse material layer including a first oxide layer of non-uniform thickness having its thinnest portion directly over said N- diffusion region; and an upper antifuse electrode disposed over said antifuse material layer; wherein said antifuse is adapted to rupture within a second area much smaller than said first area, said second area being at a predetermined location within said antifuse cell opening and located above said N- diffusion region.
Claim 7
Dependent Claim
139 words
An antifuse comprising: a lower antifuse electrode including an N- diffusion region disposed adjacent to and in contact with an N+ diffusion region; an isolation oxide layer disposed over said lower antifuse electrode; an antifuse cell opening of a first area in and through said isolation oxide layer; an antifuse material layer disposed in said antifuse cell opening and over and in physical contact with said N- diffusion region, said antifuse material layer including a first oxide layer of non-uniform thickness having its thinnest portion directly over said N- diffusion region; and an upper antifuse electrode disposed over said antifuse material layer; wherein said antifuse is adapted to rupture within a second area much smaller than said first area, said second area being at a predetermined location within said antifuse cell opening and located over said N- diffusion region.
Claim 8
Dependent Claim
139 words
An antifuse comprising: a lower antifuse electrode including an N- diffusion region disposed adjacent to and in contact with an N+ diffusion region; an isolation oxide layer disposed over said lower antifuse electrode; an antifuse cell opening of a first area in and through said isolation oxide layer; an antifuse material layer disposed in said antifuse cell opening and over and in physical contact with said N- diffusion region, said antifuse material layer including a first oxide layer of non-uniform thickness having its thinnest portion directly over said N- diffusion region; and an upper antifuse electrode disposed over said antifuse material layer; wherein said antifuse is adapted to rupture within a second area much smaller than said first area, said second area being at a predetermined location within said antifuse cell opening and located over said N- diffusion region.
Claim 9
Dependent Claim
111 words
An antifuse disposed over a semiconductor substrate comprising: a lower antifuse electrode including an N+ diffusion region and an N- diffusion region disposed within said N+ diffusion region; an isolation oxide layer disposed over said lower antifuse electrode; an antifuse cell opening in and through said isolation oxide layer; an antifuse material layer disposed in said antifuse cell opening, said antifuse material layer comprising a first oxide layer disposed over and in contact with said N- diffusion region, said first oxide layer having a non-uniform thickness with its thinnest portion located over said N- diffusion region; an upper antifuse electrode disposed over and in electrical contact with said antifuse material layer.
Claim 10
Dependent Claim
111 words
An antifuse disposed over a semiconductor substrate comprising: a lower antifuse electrode including an N+ diffusion region and an N- diffusion region disposed within said N+ diffusion region; an isolation oxide layer disposed over said lower antifuse electrode; an antifuse cell opening in and through said isolation oxide layer; an antifuse material layer disposed in said antifuse cell opening, said antifuse material layer comprising a first oxide layer disposed over and in contact with said N- diffusion region, said first oxide layer having a non-uniform thickness with its thinnest portion located over said N- diffusion region; an upper antifuse electrode disposed over and in electrical contact with said antifuse material layer.
Claim 11
Dependent Claim
18 words
An antifuse according to claim 5 wherein said antifuse cell opening is centered over said N- diffusion region.
Claim 12
Dependent Claim
34 words
An antifuse according to claim 5 wherein said antifuse material layer further comprises: a layer of nitride disposed over said first oxide layer and a second layer of oxide disposed over said nitride layer.
Claim 13
Dependent Claim
19 words
An antifuse according: to claim 5 wherein said upper antifuse electrode comprises at least one layer of doped polysilicon.
Claim 14
Dependent Claim
19 words
An antifuse according to claim 7 wherein said upper antifuse electrode comprises at least one layer of doped polysilicon.
Claim 15
Dependent Claim
41 words
An antifuse according to claim 5 wherein said upper electrode comprises a first layer of polysilicon disposed over said antifuse material layer and a second layer of doped polysilicon disposed over said isolation oxide layer and said first layer of polysilicon.
Claim 16
Dependent Claim
46 words
An antifuse according to claim 5 wherein said isolation oxide layer is of non-uniform thickness and has an oxide thickness over said N- diffusion region which is thinner than the oxide thickness over said N+ diffusion region in the range of 200 Å to 1500 Å.
Claim 17
Dependent Claim
41 words
An antifuse according to claim 5 wherein said first oxide layer has an oxide thickness over said N- diffusion region which is thinner than the oxide thickness over said N+ diffusion region in the range of 0.5 Å to 100 Å.
Claim 18
Dependent Claim
21 words
An antifuse according to claim 5 wherein said N- diffusion region has a width within the range of 0.01 μm-0.9 μm.
Claim 19
Dependent Claim
21 words
An antifuse according to claim 12 wherein said N- diffusion region has a width within the range of 0.01 μm-0.9 μm.
Claim 20
Dependent Claim
115 words
An antifuse disposed over a silicon substrate comprising: a lower antifuse electrode including an N- diffusion region disposed within, surrounded by and in contact with an N+ diffusion region disposed generally about a vertical axis of said N- diffusion region; an isolation oxide layer disposed over said lower antifuse electrode; an antifuse cell opening in and through said isolation oxide layer; an antifuse material layer disposed in said antifuse cell opening and over and in physical contact with said N- diffusion region, said antifuse material layer including a first oxide layer of non-uniform thickiness having its thinnest portion directly over said N- diffusion region; and an upper antifuse elecitrode disposed over said antifuse material layer.
Claim 21
Dependent Claim
115 words
An antifuse disposed over a silicon substrate comprising: a lower antifuse electrode including an N- diffusion region disposed within, surrounded by and in contact with an N+ diffusion region disposed generally about a vertical axis of said N- diffusion region; an isolation oxide layer disposed over said lower antifuse electrode; an antifuse cell opening in and through said isolation oxide layer; an antifuse material layer disposed in said antifuse cell opening and over and in physical contact with said N- diffusion region, said antifuse material layer including a first oxide layer of non-uniform thickiness having its thinnest portion directly over said N- diffusion region; and an upper antifuse elecitrode disposed over said antifuse material layer.
Claim 22
Dependent Claim
34 words
An antifuse according to claim 15 wherein said antifuse material layer further comprises: a layer of nitride disposed over said first oxide layer and a second layer of oxide disposed over said nitride layer.
Claim 23
Dependent Claim
17 words
An antifuse according to claim 15 wherein said upper antifuse electrode comprises a layer of doped polysilicon.
Claim 24
Dependent Claim
17 words
An antifuse according to claim 16 wherein said upper antifuse electrode comprises a layer of doped polysilicon.
Claim 25
Dependent Claim
46 words
An antifuse according to claim 15 wherein said isolation oxide layer is of non-uniform thickness and has an oxide thickness over said N- diffusion region which is thinner than the oxide thickness over said N+ diffusion region in the range of 200 Å to 1500 Å.
Claim 26
Dependent Claim
41 words
An antifuse according to claim 15 wherein said first oxide layer has an oxide thickness over said N- diffusion region which is thinner than the oxide thickness over said N+ diffusion region in the range of 0.5 Å to 100 Å.
Claim 27
Dependent Claim
21 words
An antifuse according to claim 15 wherein said N- diffusion region has a width within the range of 0.01 μm-0.9 μm.
Claim 28
Dependent Claim
20 words
An antifuse according to claim 20 wherein said N- diffusion region has a width within the range of 0.01μm-0.9 μm.
Claim 29
Independent Claim
261 words
A method of fabricating an antifuse comprising the following: (a) performing a blanket N- implant over a first region of a semiconductor substrate; (b) performing an N- drive-in; (c) forming an N+ implant mask over a first portion of said first region; (d) performing an N+ implant into a second portion of said first region not protected by said N+ implant mask and surrounding said N+ implant mask, said N+ implant forming an N+ region surrounding and in contact with said first portion of said first region; (e) removing said implant mask; (f) performing an N+ anneal and drive-in to form an N+ diffusion region in and adjacent to said second portion and leaving an N- diffusion region within said first region surrounded by said N+ diffusion region; (g) forming an isolation oxide layer over said first and second portion; (h) masking with a cell open mask and etching said isolation oxide layer to open an antifuse cell opening therein exposing at least a portion of said N+ diffusion region and at least a portion of said N- diffusion region; (i) forming an antifuse material layer in said antifuse cell opening including the formation of a first oxide layer over and in contact with said at least a portion of said N+ diffusion region and said at least a portion of said N- diffusion region, said first oxide layer having a non-uniform thickness with its thinnest part located over said at least a portion of said N- diffusion region; and (j) forming an upper antifuse electrode over said antifuse material layer.
Claim 30
Independent Claim
261 words
A method of fabricating an antifuse comprising the following: (a) performing a blanket N- implant over a first region of a semiconductor substrate; (b) performing an N- drive-in; (c) forming an N+ implant mask over a first portion of said first region; (d) performing an N+ implant into a second portion of said first region not protected by said N+ implant mask and surrounding said N+ implant mask, said N+ implant forming an N+ region surrounding and in contact with said first portion of said first region; (e) removing said implant mask; (f) performing an N+ anneal and drive-in to form an N+ diffusion region in and adjacent to said second portion and leaving an N- diffusion region within said first region surrounded by said N+ diffusion region; (g) forming an isolation oxide layer over said first and second portion; (h) masking with a cell open mask and etching said isolation oxide layer to open an antifuse cell opening therein exposing at least a portion of said N+ diffusion region and at least a portion of said N- diffusion region; (i) forming an antifuse material layer in said antifuse cell opening including the formation of a first oxide layer over and in contact with said at least a portion of said N+ diffusion region and said at least a portion of said N- diffusion region, said first oxide layer having a non-uniform thickness with its thinnest part located over said at least a portion of said N- diffusion region; and (j) forming an upper antifuse electrode over said antifuse material layer.
Claim 31
Independent Claim
263 words
A method of fabricating an antifuse comprising the following: (a) forming an N- diffusion region over a first region of a semiconductor substrate; (b) forming an implant mask over and protecting a first portion of said first region; (c) implanting an N+ region into a second portion of said first region surrounding and not protected by said N+ implant mask; (d) removing said implant mask; (e) forming an N+ dififusion region in and adjacent to said second portion of said first region and leaving an N- diffusion region within said first portion of said first region, said N+ diffusion region surrounding and in contact with said N- diffusion region; (f) forming an isolation oxide layer over said first and second portion of said first region; (g) masking with a cell open mask and etching said isolation oxide layer to open an antifuse cell opening therein exposing at least a portion of said N+ diffusion region and at least a portion of said N- diffusion region, said exposed portion of said N+ diffusion region surrounding said exposed portion of said N- diffusion region; (h) forming an antifuse material layer in said antifuse cell opening including the formation of a first oxide layer over and in contact with said at least a portion of said N+ diffusion region and said at least a portion of said N- diffusion region, said first oxide layer having a non-uniform thickness with its thinnest part located over said at least a portion of said N- diffusion region; and (i) forming an upper antifuse electrode over said antifuse material layer.
Claim 32
Independent Claim
263 words
A method of fabricating an antifuse comprising the following: (a) forming an N- diffusion region over a first region of a semiconductor substrate; (b) forming an implant mask over and protecting a first portion of said first region; (c) implanting an N+ region into a second portion of said first region surrounding and not protected by said N+ implant mask; (d) removing said implant mask; (e) forming an N+ dififusion region in and adjacent to said second portion of said first region and leaving an N- diffusion region within said first portion of said first region, said N+ diffusion region surrounding and in contact with said N- diffusion region; (f) forming an isolation oxide layer over said first and second portion of said first region; (g) masking with a cell open mask and etching said isolation oxide layer to open an antifuse cell opening therein exposing at least a portion of said N+ diffusion region and at least a portion of said N- diffusion region, said exposed portion of said N+ diffusion region surrounding said exposed portion of said N- diffusion region; (h) forming an antifuse material layer in said antifuse cell opening including the formation of a first oxide layer over and in contact with said at least a portion of said N+ diffusion region and said at least a portion of said N- diffusion region, said first oxide layer having a non-uniform thickness with its thinnest part located over said at least a portion of said N- diffusion region; and (i) forming an upper antifuse electrode over said antifuse material layer.
Claim 33
Independent Claim
234 words
A method of fabricating an antifuse comprising the following: (a) forming an N- diffusion region over a first region of a semiconductor substrate; (b) forming an implant mask over and protecting a first portion of said first region; (c) implanting an N+ region into a second portion of said first region surrounding and not protected by said N+ implant mask; (d) removing said implant mask; (e) forming an N+ diffusion region in and adjacent to said second portion of said first region and leaving an N- diffusion region within said first portion of said first region; (f) forming an isolation oxide layer over said first and second portion of said first region; (g) wet oxide etching without a fuse cell open mask said isolation oxide layer to open an antifuse cell opening therein exposing at least a portion of said N+ diffusion region and at least a portion of said N- diffusion region; (h) forming an antifuse material layer in said antifuse cell opening including the formation of a first oxide layer over and in contact with said at least a portion of said N+ diffusion regions and said at least a portion of said N- diffusion region, said first oxide layer having a non-uniform thickness with its thinnest part located over said at least a portion of said N- diffusion region; and (i) forming an upper antifuse electrode over said antifuse material layer.
Claim 34
Independent Claim
234 words
A method of fabricating an antifuse comprising the following: (a) forming an N- diffusion region over a first region of a semiconductor substrate; (b) forming an implant mask over and protecting a first portion of said first region; (c) implanting an N+ region into a second portion of said first region surrounding and not protected by said N+ implant mask; (d) removing said implant mask; (e) forming an N+ diffusion region in and adjacent to said second portion of said first region and leaving an N- diffusion region within said first portion of said first region; (f) forming an isolation oxide layer over said first and second portion of said first region; (g) wet oxide etching without a fuse cell open mask said isolation oxide layer to open an antifuse cell opening therein exposing at least a portion of said N+ diffusion region and at least a portion of said N- diffusion region; (h) forming an antifuse material layer in said antifuse cell opening including the formation of a first oxide layer over and in contact with said at least a portion of said N+ diffusion regions and said at least a portion of said N- diffusion region, said first oxide layer having a non-uniform thickness with its thinnest part located over said at least a portion of said N- diffusion region; and (i) forming an upper antifuse electrode over said antifuse material layer.
Claim 35
Dependent Claim
43 words
A method of fabricating an antifuse according to claim 23 wherein said cell open mask has an opening in the range of 0.05 μm to 1.00 μm larger in dimension than the width of said N- diffusion region thus providing alignment tolerant capability.
Claim 36
Dependent Claim
43 words
A method of fabricating an antifuse according to claim 24 wherein said cell open mask has an opening in the range of 0.05 μm to 1.00 μm larger in dimension than the width of said N- diffusion region thus providing alignment tolerant capability.
References Cited (Backward Citations)
US4851364A
Cited
US4748490A
Cited
US4823181A
Cited
US4899205A
Cited
US5266829A
Cited
US5134457A
Cited
US4868138A
Cited
US4866001A
Cited
EP0416903A2
Cited
US5223217A
Cited
US5070384A
Cited
US5057451A
Cited
US5061646A
Cited
US4997790A
Cited
US5087958A
Cited
US5163180A
Cited
US5166556A
Cited
US5196724A
Cited
US5290734A
Cited
US5110754A
Cited
US5171715A
Cited
US5208177A
Cited
US5282158A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |