US5619062A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Personalizable gate array devices
Assignee: Chip Express Israel Ltd
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Filing: 1995-03-14
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Granted: 1997-04-08
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Expires: 2015-03-14
Abstract
Abstract Customizable semiconductor devices, integrated circuit gate arrays and techniques to produce same are disclosed. The devices comprise integrated circuit blanks having a collection of semiconductor elements and at least one metal layer including fusible links interconnecting said collection of semiconductor elements into an inoperably connected integrated circuit blank. At least one metal layer is first etched thereby to define a pattern of conductors. A passivation layer is provided over at least one metal layer, afterwhich at least one metal layer is etched a second time for selectably removing the fusible links, thereby converting the inoperable integrated circuit blank into a selected operable electronic function.
Inventors
- 👤 Meir I. Janai
- 👤 Zvi Orbach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:41
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D86/00; H10W20/49; H10W20/493; H10W20/494
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
105 words
A device having a plurality of accessible input/output pins comprising: a substrate; a plurality of transistors provided on said substrate; and a plurality of links connecting the transistors into an inoperable circuit, at least some of said plurality of links having designated fuse locations, said plurality of links and transistors being arranged such that, upon disconnecting of selected ones of said plurality of links at ones of said designated fuse locations, said plurality of links and transistors is interconnected into an operable CMOS gate array circuit, wherein said fuse locations are not selectively fusible by current supplied at said accessible input/output pins of the device.
Claim 2
Independent Claim
105 words
A device having a plurality of accessible input/output pins comprising: a substrate; a plurality of transistors provided on said substrate; and a plurality of links connecting the transistors into an inoperable circuit, at least some of said plurality of links having designated fuse locations, said plurality of links and transistors being arranged such that, upon disconnecting of selected ones of said plurality of links at ones of said designated fuse locations, said plurality of links and transistors is interconnected into an operable CMOS gate array circuit, wherein said fuse locations are not selectively fusible by current supplied at said accessible input/output pins of the device.
Claim 3
Dependent Claim
30 words
A device according to claim 1, wherein said links with said fusible locations are formed in a plurality of metal layers, adjacent metal layers being separated by an insulation layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |