EP0303396A1
Expired / Lapsed
EP
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Improved laser-blown links
Assignee: AT&T Inc
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Filing: 1988-08-03
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Granted: —
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Expires: 2008-08-03
Abstract
Abstract An improved technique for blowing conductive links with a laser provides for a wider range of acceptable laser energies. The link in an upper interconnect level is placed on a pedestal, typically formed by etching away a thin layer of the underlying dielectric on which he conductive link is formed. A link in a lower interconnect level thereby has the thickness of the dielectric overlying it reduced. This has been found to reduce the minimum laser energy required to cleanly blow the links in both levels and to reduce the effect of link orientation on the required laser energy.
Inventors
- 👤 Frederick Harrison Fischer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 10:20
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10W20/494
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
108 words
A solid state circuit comprising a lower interconnect level having a conductive link (e.g., 12) adapted to being rendered non-conductive by the application of radiant energy thereto, wherein said interconnect level is overlaid by a dielectric layer (e.g., 13) that is overlaid by an upper interconnect level (e.g., 14) which crosses over said lower interconnect level at crossover locations (e.g., 25), CHARACTERIZED in that an etch-resistant masking layer (e.g., 23) is formed over at least said crossover locations, and the thickness of said dielectric layer over said link in the lower interconnect level is substantially less than the thickness of said dielectric layer under said etch-resistant masking layer.
Claim 2
Dependent Claim
108 words
A solid state circuit comprising a lower interconnect level having a conductive link (e.g., 12) adapted to being rendered non-conductive by the application of radiant energy thereto, wherein said interconnect level is overlaid by a dielectric layer (e.g., 13) that is overlaid by an upper interconnect level (e.g., 14) which crosses over said lower interconnect level at crossover locations (e.g., 25), CHARACTERIZED in that an etch-resistant masking layer (e.g., 23) is formed over at least said crossover locations, and the thickness of said dielectric layer over said link in the lower interconnect level is substantially less than the thickness of said dielectric layer under said etch-resistant masking layer.
Claim 3
Dependent Claim
32 words
The circuit of claim 1 wherein the thickness of said dielectric layer over said link is at least 25 nanometers less than the thickness of said dielectric layer under said masking layer.
Claim 4
Dependent Claim
11 words
The circuit of claim 1 wherein said link is a metal.
Claim 5
Dependent Claim
10 words
The circuit of claim 3 wherein said link is aluminum.
Claim 6
Dependent Claim
10 words
The circuit of claim 3 wherein said link is gold.
Claim 7
Dependent Claim
12 words
The circuit of claim 3 wherein said link comprises a metal silicide.
Claim 8
Dependent Claim
11 words
The circuit of claim 6 wherein said silicide is titanium silicide.
Claim 9
Dependent Claim
11 words
The circuit of claim 1 wherein said link comprises doped polysilicon.
Claim 10
Dependent Claim
14 words
The circuit of claim 1 wherein said dielectric layer is a glass comprising phosphorus.
References Cited (Backward Citations)
EP0089814A2
Cited
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