US5572053A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory cell having a stacked capacitor
Assignee: Fujitsu Ltd
•
Filing: 1994-08-16
•
Granted: 1996-11-05
•
Expires: 2014-08-16
Abstract
Abstract A DRAM device includes bit lines formed on an interlayer insulation film which covers gate electrodes on an insulation film on a semiconductor substrate. Each bit line is in contact with the corresponding source region formed in the substrate through an opening in the insulation films. Another insulation film is formed so as to cover the bit lines. A storage electrode is formed on the insulation film covering the bit line, and is in contact with a drain region in the substrate through another opening in the insulation films. The bit line has a vertical layer level lower than that of the storage electrode. The storage electrode is covered with a dielectric film, which is covered with an opposed electrode.
Inventors
- 👤 Taiji Ema
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:45
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/48; H10B12/482; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/31; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
210 words
A dynamic random access memory comprising: a plurality of dynamic type memory cells, each of said plurality of dynamic type memory cells including: a transfer gate transistor having a source region and a drain region formed in a semiconductor substrate, and a gate electrode; and a memory cell capacitor; a first insulating film formed over the semiconductor substrate; word lines covered by said first insulating film, said gate electrode being connected to one of said word lines; pairs of bit lines formed over said first insulating film, intersections being formed at cross points of said word lines and said bit lines, said bit lines contacting source regions of said transfer gate transistors of said dynamic type memory cells at every other cross point of said bit lines and word lines; and a second insulating film covering said pairs of bit lines; said memory cell capacitor comprising: a storage electrode contacting said drain region and extending over said second insulating film, said bit lines being located at a layer level lower than said storage electrode; a dielectric film formed around said storage electrode; and an opposed electrode covering said storage electrode through said dielectric film, said opposed electrode having a portion located between said first insulating film and said storage electrode.
Claim 2
Dependent Claim
210 words
A dynamic random access memory comprising: a plurality of dynamic type memory cells, each of said plurality of dynamic type memory cells including: a transfer gate transistor having a source region and a drain region formed in a semiconductor substrate, and a gate electrode; and a memory cell capacitor; a first insulating film formed over the semiconductor substrate; word lines covered by said first insulating film, said gate electrode being connected to one of said word lines; pairs of bit lines formed over said first insulating film, intersections being formed at cross points of said word lines and said bit lines, said bit lines contacting source regions of said transfer gate transistors of said dynamic type memory cells at every other cross point of said bit lines and word lines; and a second insulating film covering said pairs of bit lines; said memory cell capacitor comprising: a storage electrode contacting said drain region and extending over said second insulating film, said bit lines being located at a layer level lower than said storage electrode; a dielectric film formed around said storage electrode; and an opposed electrode covering said storage electrode through said dielectric film, said opposed electrode having a portion located between said first insulating film and said storage electrode.
Claim 3
Dependent Claim
70 words
A dynamic random access memory as claimed in claim 1, wherein: said word lines extend in a first direction; said source regions and said drain regions are arranged along a second direction substantially perpendicular to the first direction; and said bit lines extend in the second direction and include branch portions located in a vicinity of said source regions, said branch portions of said bit lines contact said source regions.
Claim 4
Dependent Claim
20 words
A dynamic random access memory as claimed in claim 2, wherein said word lines have bent portions at said intersections.
Claim 5
Dependent Claim
36 words
A dynamic random access memory as claimed in claim 2, wherein: said source regions have portions extending in the first direction; and said branch portions of said bit lines contact said portions of said source regions.
Claim 6
Dependent Claim
20 words
A dynamic random access memory as claimed in claim 4, wherein said word lines have bent portions at said intersections.
Claim 7
Dependent Claim
237 words
A dynamic random access memory comprising: a plurality of dynamic type memory cells, each of said plurality of dynamic type memory cells including: a transfer gate transistor having a source region and a drain region formed in a semiconductor substrate, and a gate electrode; and a memory cell capacitor; a first insulating film formed over the semiconductor substrate; word lines covered by said first insulating film, said gate electrode being connected to one of said word lines; pairs of bit lines formed over said first insulating film, intersections being formed at cross points of said word lines and said bit lines, said bit lines contacting said source regions of said transfer gate transistors of said dynamic type memory cells at every other cross point of said bit lines and word lines; and a second insulating film covering said pairs of bit lines; said memory cell capacitor comprising: a storage electrode contacting said drain region and extending over said second insulating film, said bit lines being located at a layer level lower than said storage electrode, said storage electrode having a vertical portion contacting said drain region and having wing portions spaced apart from each other and connected to said vertical portion; a dielectric film formed around said storage electrode; and an opposed electrode covering said storage electrode through said dielectric film, said opposed electrode having a portion located between said first insulating layer and said storage electrode.
Claim 8
Dependent Claim
237 words
A dynamic random access memory comprising: a plurality of dynamic type memory cells, each of said plurality of dynamic type memory cells including: a transfer gate transistor having a source region and a drain region formed in a semiconductor substrate, and a gate electrode; and a memory cell capacitor; a first insulating film formed over the semiconductor substrate; word lines covered by said first insulating film, said gate electrode being connected to one of said word lines; pairs of bit lines formed over said first insulating film, intersections being formed at cross points of said word lines and said bit lines, said bit lines contacting said source regions of said transfer gate transistors of said dynamic type memory cells at every other cross point of said bit lines and word lines; and a second insulating film covering said pairs of bit lines; said memory cell capacitor comprising: a storage electrode contacting said drain region and extending over said second insulating film, said bit lines being located at a layer level lower than said storage electrode, said storage electrode having a vertical portion contacting said drain region and having wing portions spaced apart from each other and connected to said vertical portion; a dielectric film formed around said storage electrode; and an opposed electrode covering said storage electrode through said dielectric film, said opposed electrode having a portion located between said first insulating layer and said storage electrode.
Claim 9
Dependent Claim
70 words
A dynamic random access memory as claimed in claim 6, wherein: said word lines extend in a first direction; said source regions and said drain regions are arranged along a second direction substantially perpendicular to the first direction; and said bit lines extend in the second direction and include branch portions located in a vicinity of said source regions, said branch portions of said bit lines contact said source regions.
Claim 10
Dependent Claim
20 words
A dynamic random access memory as claimed in claim 7, wherein said word lines have bent portions at said intersections.
Claim 11
Dependent Claim
36 words
A dynamic random access memory as claimed in claim 7, wherein: said source regions have portions extending in the first direction; and said branch portions of said bit lines contact said portions of said source regions.
Claim 12
Dependent Claim
20 words
A dynamic random access memory as claimed in claim 9, wherein said word lines have bent portions at said intersections.
References Cited (Backward Citations)
JPS5658254A
Cited
US4493056A
Cited
JPS59231841A
Cited
JPS59231851A
Cited
EP0161850A1
Cited
US4715015A
Cited
US4651183A
Cited
US4800525A
Cited
EP0191612A2
Cited
JPS61258467A
Cited
JPS6286853A
Cited
US4794563A
Cited
US4742018A
Cited
JPS62286269A
Cited
JPS63278363A
Cited
US4974040A
Cited
US4953126A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |